×

Multiprocessor system including a cache memory with tag copy units

  • US 5,375,220 A
  • Filed: 06/30/1992
  • Issued: 12/20/1994
  • Est. Priority Date: 07/04/1991
  • Status: Expired due to Term
First Claim
Patent Images

1. A multiprocessor computer system comprising:

  • a) first memory means for storing data, a first part of a logical address space of the computer system being assigned to the first memory means;

    b) second memory means for storing data, a second part of the logical address space of the computer system being assigned to the second memory means;

    c) first processor means, which is accessible to either of the first and second parts of the logical address space, for performing a processor operation using the logical address space;

    d) second processor means, which is accessible to either of the first and second parts of the logical address space, for performing a processor operation using the logical address space;

    e) first cache means for, when said first processor means accesses one of said first and second memory means, holding data transferred by an access between said first processor means and one of said first and second memory means, and holding first tag information showing an address to be allocated to the transferred data;

    f) second cache means for, when said second processor means accesses one of said first and second memory means, holding data transferred by an access between said second processor means and one of said first and second memory means, and holding second tag information showing an address to be allocated to the transferred data;

    g) selectively connecting means for selectively connecting said first processor means to one or both of said first and second memory means, and selectively connecting said second processor means to one or both of said first and second memory means;

    h) first tag copying means, coupled to a node between said selectively connecting means and said first memory means, for holding a copy of each of the first and second tag information;

    i) second tag copying means, coupled to a node between said selectively connecting means and said second memory means, for holding a copy of each of the first and second tag information;

    j) first cache control means, when it is determined from the first tag information held in said first tag copying means that, due to the access to said first memory means, by said second processor means a content of the accessed logical address space differs from a content of said first cache means, for preventing said first processor means from using the content of said first cache means; and

    k) second cache control means, when it is determined from the second tag information held in said second tag copying means that, due to the access to said second memory means by said first processor means, a content of the accessed logical address differs from a content of said second cache means, for preventing said second processor means from using the content of said second cache means.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×