Back-up power supply apparatus for protection of stored data

• US 5,375,246 A
• Filed: 08/26/1991
• Issued: 12/20/1994
• Est. Priority Date: 08/30/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kimura, Kazumasa, Hiramoto, Masato
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): DAVIS, GEORGE B
• Application Number:
  US07/749,443
• Time in Patent Office: 1,212 Days
• Field of Search: 395/750, 365/226, 365/227, 365/229, 364/431.11, 364/483, 364/492, 371/66, 371/9.1
• US Class Current: 365/229
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A stored data protection apparatus for an electronic device has a CPU (20) and a volatile memory (21) controlled by the CPU for storing data therein. Both of the CPU and the volatile memory ace supplied power voltage from a main battery (22) in normal operation of the device. The volatile memory as supplied power voltage from a back-up battery (23) when the main battery is removed from the device. The apparatus has a switch (29) operable in first and second positions, taking the first position in the normal operation of the device, and being switched from the first position to the second position when the main battery is removed from the device, a circuit (44, 48) for inhibiting the CPU to access the volatile memory when the switch is in the second position, and a circuit (38, 34, 42, 43) for releasing the inhibition of the CPU by the inhibiting circuit when the switch is switched from the second position to the first position.

Claims

1. A stored data protection apparatus for an electronic device, said device having a CPU and a volatile memory which is controlled with an enabling signal from said CPU for storing data therein, both of said CPU and said volatile memory being supplied power voltage from a main battery when said main battery is connected in said device, and said volatile memory being supplied power voltage from a back-up battery when said main battery is removed from said device so as to prevent the data stored in the volatile memory from being destroyed, said apparatus comprising:

a switching means operable between a first position and a second position, and taking the first position when said main battery is connected in said device, and being switched from the first position to the second position prior to said main battery being removed from said device, including

means for supplying an off signal to the CPU when said switching means is switched to the second position, said CPU supplying setting signals to said stored data protection apparatus and shifting to a standby mode upon receiving said off signal;

means for inhibiting said CPU from accessing said volatile memory in response to said switching means being in the second position, including

a gate means connected to said CPU for receiving said enabling signal from said CPU and supplying the enabling signal to said volatile memory when said switching means is in the first position, and

a flip-flop means for preventing said gate means from supplying said enabling signal to said volatile memory when said switching means is in the second position, said flip-flop means being connected to receive said setting signals and to be set by said setting signals from said CPU to prevent said gate means from supplying said enabling signal to the volatile memory; and

means for releasing an accessing inhibition of said CPU by means of said inhibiting means in response to said switching means being switched from the second position to the first position, including

a pulse generating means for generating a reset pulse to be supplied to said flip-flop means to reset said flip-flop means and to said CPU to reset said CPU in response to said switching means being switched from the second position to the first position.

2. An apparatus as claimed in claim 1, wherein said switching means includes a switch being kept in an on state during a replacement operation of said main battery and in an off state when said main battery is connected in said device.

3. An apparatus as claimed in claim 2, wherein said means for releasing includes logic means responsive to said reset pulse and being connected to said CPU so as to reset said CPU in response to said switch being switched from the second position to the first position.

4. An apparatus as claimed in claim 1, wherein said apparatus further comprises a first detection means for detecting that power supply voltage from said main battery is lower than a first predetermined voltage, and a release preventing means for preventing said releasing means from releasing the inhibition of said CPU when said first detection means detects that said power supply voltage is lower than said first predetermined voltage.

5. An apparatus as claimed in claim 4, wherein said inhibiting means further includes a second detection means for detecting that power supply voltage from said back-up battery is lower than a second predetermined voltage, and means for preventing said flip-flop means from being reset when said second detecting means detects that said power supply voltage is lower than said second predetermined voltage.