N-channel field effect transistor having an oblique arsenic implant for lowered series resistance

• US 5,376,566 A
• Filed: 11/12/1993
• Issued: 12/27/1994
• Est. Priority Date: 11/12/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/152,116
• Time in Patent Office: 410 Days
• Field of Search: 437/35, 437/44, 437/27, 437/52, 437/60, 437/919
• US Class Current: 438/253
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

An improved N-channel field-effect transistor is fabricated by performing a vertical N- implant, aligned to the vertical edges of the gate electrode, in both the source and drain regions of the device. In a first embodiment of the invention intended for use in dynamic random access memory access devices, a dielectric spacer is then formed on the sidewall of the gate electrode adjacent the drain (i.e., the regions which functions as the bitline contact in a DRAM memory cell). A vertical N+ implant, aligned to the exposed vertical edge of that spacer, is performed, in addition to an oblique implant of an N-type impurity. The oblique implant dosage is significantly greater than the N- implant dosage, but significantly less than the N+ implant dosage. In a second embodiment of the invention intended for use in applications where the transistor has no capacitive storage node, spacers are formed on both sidewalls of the gate electrode and the N+ implant, as well as the oblique N-type implant are performed in both the source and drain regions of the device. In preferred embodiments of the invention, phosphorus is utilized as the N- implant impurity, while arsenic is utilized for the other two N-type implants. The oblique implant provides not only reduced electric field strength in the channel region, but also reduced series resistance.

Claims

1. A process for fabricating an improved N-channel field effect transistor for use as an access device in a dynamic random access memory cell, said transistor having a first source/drain region which functions as a bitline contact region and a second source/drain region which functions as a storage node, said process comprising the following steps:

(a) implanting a P-type impurity aligned to the physical limits of the gate electrode;

(b) forming a first dielectric layer on at least the exposed vertical surfaces of the gate electrode;

(c) performing a first implanting of an N-type impurity that is aligned to the exposed surfaces of portions of the dielectric layer covering the exposed vertical surfaces of the gate electrode;

(d) conformally depositing a second dielectric layer;

(e) anisotropically etching said first and second dielectric layers to form spacers on the vertical surfaces of the gate electrode;

(f) constructing a cell capacitor superjacent the storage node source/drain region;

(g) performing a second implanting of an N-type impurity that is aligned to the physical limits of the spacer in the bitline contact source/drain region, the cell capacitor preventing implanting of the N-type impurity in the storage node source/drain region during the second implanting; and

(h) performing a third implanting of an N-type impurity, said third implanting being performed obliquely, the cell capacitor preventing implanting of the N-type impurity in the storage node source/drain region during the third implanting.

2. The process of claim 1, wherein the first implanting utilizes phosphorus as the impurity.

3. The process of claim 1, wherein said second and third implantings utilize arsenic as the impurity.

4. The process of claim 1, wherein steps (a) through (g) are performed in sequence, with step (a) being the first step.

5. The process of claim 1, wherein steps (a) through (f) are performed in sequence, with step (a) being the first step, and step (h) follows step (f), and step (g) follows step (h).

6. The process of claim 2, wherein the phosphorus is implanted at a dosage within a range of 1 to 2×

10¹³ atoms/cm², and at an energy level within a range of 100 to 130 Kev.

7. The process of claim 3, wherein the arsenic used in said second implanting is implanted at a dosage within a range of 4×

10¹⁵ to 1.2×

10¹⁶ atoms/cm², and at an energy level within a range of 30 to 60 Kev.

8. The process of claim 3, wherein the arsenic used in said third implanting is implanted at a dosage within a range of 3×

10¹³ to 1×

10¹⁵ atoms/cm², and at an energy level within a range of 80 to 120 Kev.

9. The process of claim 1, wherein the third implanting is performed at an angle within a range of 30 to 50 degrees from the horizontal.

10. The process of claim 1, wherein the preferred angle for the third implanting is about 40 degrees from the horizontal.