Amplifier with gain stages coupled for differential error correction

• US 5,376,899 A
• Filed: 02/04/1994
• Issued: 12/27/1994
• Est. Priority Date: 02/04/1994
• Status: Expired due to Term

• Current Assignee: Pass Laboratories, Inc.
• Original Assignee: Pass Laboratories, Inc.
• Inventors: Pass, Nelson S.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/192,173
• Time in Patent Office: 326 Days
• Field of Search: 330/69, 330/253, 330/255, 330/264, 330/277, 330/124 R
• US Class Current: 330/253
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 2203/45116 Feedback coupled to the input of the differential amplifier
• CPC Class Codes: H03F 3/45206 Folded cascode stages

Abstract

An amplifier circuit having two identical inverting folded-cascode amplifier stages coupled together through a coupling resistor at the positive terminals of the respective stages. Each stage includes an input gain transistor whose gate forms the negative input terminal of the amplifier stage coupled to receive an input signal through an input resistor, whose source forms the positive input terminal of the amplifier stage, and whose drain is connected to the source of a level-shifting cascode transistor. Both transistors are supplied current from a constant current source also connected to the source of the level-shifting transistor. The drain of the level-shifting transistor forms an output terminal of the amplifier stage. Each stage feeds its amplifier output negatively to the positive input of the other stage, while at the same time feeding its distortion and noise contribution positively, via input gain transistor conduction, to the other stage. Balanced amplified outputs are produced from either balanced or unbalanced inputs, and distortion and noise components are produced in common on both outputs for differential cancellation. Complementary-symmetry and power amplifier versions of the basic single-ended line-level amplifier are also provided.

Claims

1. An amplifier circuit comprising

a first inverting amplifier stage having a first input terminal, a first coupling terminal and a first output terminal, said first inverting amplifier stage also having a first input resistor connected to said first input terminal and a first feedback resistor connected between said first output terminal and said first input terminal,

a second inverting amplifier stage having a second input terminal, a second coupling terminal and a second output terminal, said second inverting amplifier stage also having a second input resistor connected to said second input terminal and a second feedback resistor connected between said second output terminal and said second input terminal, said first and second inverting amplifier stages being identical, and

means for coupling said first and second coupling terminals together, each of said first and second coupling terminals acting simultaneously as a positive input terminal of its corresponding amplifier stage, a complementary output of the corresponding amplifier stage for negative signal coupling to the other amplifier stage, and means for positively communicating distortion and noise contributions of the corresponding amplifier stage to the other amplifier stage, such that differential input signals received by said first and second input terminals are amplified and provided as balanced differential output signals on said first and second output terminals and such that distortion and noise contributions of both amplifier stages are provided in common on said first and second output terminals.

2. The amplifier circuit of claim 1 wherein each of said first and second amplifier stages is an inverting folded-cascode amplifier.

3. The amplifier circuit of claim 2 wherein said inverting folded-cascode amplifiers are complementary-symmetry (push-pull) amplifiers.

4. The amplifier circuit of claim 2 wherein said inverting folded-cascode amplifiers each include a follower output device for power amplification.

5. The amplifier circuit of claim 2 wherein said inverting folded-cascode amplifiers include field-effect transistors.

6. An amplifier circuit comprising

a first inverting folded-cascode amplifier having a first input gain transistor with a source, a drain and a gate connected to a first input resistor, a first cascode level-shifting transistor with a source connected to the drain of said first input gain transistor, a drain coupled to a first output terminal, and a gate connected to a bias voltage selected to maintain said first cascode level-shifting transistor in a conducting state, a first feedback resistor connected between said first output terminal and said gate of said first input gain transistor, and a first constant current source connected to said drain of said first input gain transistor and said source of said first cascode level-shifting transistor, said first constant current source coupled to a first power supply, said source of said first input gain transistor and said drain of said first cascode level-shifting transistor coupled to a second power supply, said first and second power supplies being of balanced voltages,

a second inverting folded-cascode amplifier having a second input gain transistor with a source, a drain and a gate connected to a second input resistor, a second cascode level-shifting transistor with a source connected to the drain of said second input gain transistor, a drain coupled to a second output terminal, and a gate connected to a bias voltage selected to maintain said second cascode level-shifting transistor in a conducting state, a second feedback resistor connected between said second output terminal and said gate of said second input gain transistor, and a second constant current source connected to said drain of said second input gain transistor and said source of said second cascode level-shifting transistor, said second constant current source coupled to said first power supply, said source of said second input gain transistor and said drain of said second cascode level-shifting transistor coupled to said second power supply, said second inverting folded-cascode amplifier having substantially the same operating characteristics as said first inverting folded-cascode amplifier, and

means, connected between said sources of said first and second input gain transistors, for coupling said first inverting folded-cascode amplifier to said second inverting folded-cascode amplifier.

7. The amplifier circuit of claim 6 wherein said means for coupling includes a coupling resistor connected to said sources of said first and second input gain transistors.

8. The amplifier circuit of claim 7 wherein said means for coupling further comprises a pair of shunt resistors connected between said respective sources of said first and second input gain transistors and ground.

9. The amplifier circuit of claim 6 further comprising a first complementary (push-pull) pair of source-follower output transistors with gates biased for at least class AB conduction and coupled to said drain of said first cascode level-shifting transistor, with drains coupled to said respective first and second power supplies, and sources both connected to said first output terminal, and a second complementary (push-pull) pair of source-follower output transistors with gates biased for at least class AB conduction and coupled to said drain of said second cascode level-shifting transistor, with drains coupled to said respective first and second power supplies, and sources both connected to said second output terminal.

10. The amplifier circuit of claim 6 wherein said first and second input gain transistors are N-channel field-effect transistors and said first and second cascode level-shifting transistors are P-channel field-effect transistors.

11. The amplifier circuit of claim 6 wherein said first and second inverting folded-cascode amplifiers are complementary-symmetry amplifiers,

said first inverting folded-cascode amplifier having a third input gain transistor with a source connected to the source of said first input gain transistor, a drain and a gate connected to said first input resistor, a third cascode level-shifting transistor with a source connected to said drain of said third input gain transistor, a drain coupled to said first output terminal, and a gate connected to a bias voltage selected to maintain said third cascode level-shifting transistor in a conducting state, and a third constant current source connected to said drain of said third input gain transistor and said source of said third cascode level-shifting transistor, said third constant current source also coupled to said second power supply,

said second inverting folded-cascode amplifier having a fourth input gain transistor with a source connected to the source of said second input gain transistor, a drain, and a gate connected to said second input resistor, a fourth cascode level-shifting transistor with a source connected to said drain of said fourth input gain transistor, a drain coupled to said second output terminal, and a gate connected to a bias voltage selected to maintain said fourth cascode level-shifting transistor in a conducting state, and a fourth constant current source connected to said drain of said fourth input gain transistor and said source of said fourth cascode level-shifting transistor, said fourth constant current source also coupled to said second power supply.

12. The amplifier circuit of claim 11 further comprising a first complementary (push-pull) pair of source-follower output transistors with gates biased for at least class AB conduction and coupled to said drains of said respective first and third cascode level-shifting transistors, with drains coupled to said respective first and second power supplies, and with sources both connected to said first output terminal, and a second complementary (push-pull) pair of source-follower output transistors with gates biased for at least class AB conduction and coupled to said drains of said respective second and fourth cascode level-shifting transistors, with drains coupled to said respective first and second power supplies, and with sources both connected to said second output terminal.

13. The amplifier circuit of claim 6 wherein said sources of said first and second input gain transistors and said drains of said first and second cascode level-shifting transistors are respectively coupled to said second power supply via an additional four constant current sources.