One-bit switched-capacitor D/A circuit with continuous time linearity

• US 5,376,936 A
• Filed: 06/16/1993
• Issued: 12/27/1994
• Est. Priority Date: 06/16/1993
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Inventors: Kasha, Dan B., Kerth, Donald A.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/078,591
• Time in Patent Office: 559 Days
• Field of Search: 341/150, 341/144, 341/152, 341/155, 341/172, 341/166
• US Class Current: 341/150
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation

Abstract

A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle φ₂. A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the φ₂ cycle provides an integrated output that is slew-limited. The full charge of the selected capacitor (78) or (94) is allowed to be completely dumped onto the node (48) prior to the output switched capacitor (54) being disposed across the feedback capacitor (50). This allows for a linear operation in this range. Thereafter, the charge is passively distributed across the feedback capacitor (50) in a linear fashion associated with the lossy integrator. This provides a conversion from a digital signal one-bit data stream to a continuous time output analog signal.

Claims

1. A data conversion system including digital-to-analog converter having a digital input and an analog output, the digital input for receiving a digital signal and having at least a first logic state and a second logic state, and outputting a continuous time analog output signal on the analog output, the digital-to-analog converter comprising:

a first circuit responsive to the presence of the first logic state on the digital input for causing the analog output to change in value independent of the output in accordance with a predetermined transfer function, said change in value being substantially the same each time the first logic state is present on the digital input

a second circuit responsive to the presence of the second logic state on the digital input for causing the analog output to change in value independent of the output in accordance with said predetermined transfer function, said change in value caused by said second circuit being substantially the same each time the second logic state is present, the analog output signal on the analog output having a substantially linear response in the continuous time domain due to said first and second circuits, and

a redistribution circuit operable to limit the DC gain of said predetermined transfer function to a known and fixed quantity.

2. The data conversion system of claim 1, wherein the digital signal is a one-bit digital input signal comprising a one-bit digital input data stream.

3. The data conversion system of claim 1, wherein the change in value of the analog output signal due to said first circuit is substantially equal and opposite to the change in value of the analog output signal due to said second circuit.

4. A data conversion system having a digital-to-analog converter for receiving a one-bit digital input data stream having first and second states and outputting a continuous time analog signal, the digital-to-analog converter comprising:

an integration stage having an amplifier with a summing input node and an output node, and a feedback capacitor disposed between said summing input node and said output node;

an input charging device operating in first and second modes, said input charging device in said first mode operable to input a finite amount of charge to said summing node and, in a said second mode, operable to extract a finite amount of charge from said summing node;

an output capacitance device for selectively disposing an output capacitance across said feedback capacitor to distribute the charge on said feedback capacitor between said feedback capacitor and said output capacitance; and

a switching device for controlling said input charging device to connect said input charging device to said summing node during a first time period to selectively add charge thereto or selectively extract charge therefrom, said switching device operable to select said first mode in said input charging device for the first state of the input digital data stream and to select said second mode in said input charging device for the second state of the digital input data stream, said switching device also operable to control said output capacitance device to connect said output capacitance across said feedback capacitor during a second and subsequent time period.

5. The data conversion system of claim 4, wherein said finite amount of charge input to said summing input node and said finite amount of charge extracted from said summing input node have substantially the same magnitude.

6. The data conversion system of claim 4, wherein said input charging device comprises:

a first switched-capacitor having first and second plates;

a first switching circuit operable during said second time period to switch said first plate to a positive reference voltage and said second plate to a negative reference voltage lower than said positive reference voltage and, during said first time period, switching said first plate to said negative reference voltage and said second plate to a first switching node;

a second switched capacitor having first and second plates;

a second switching circuit for controlling said second switching capacitor, and operable during said second time period to switch said first and second plates to said negative reference voltage and, during said first time period, switching said first plate to said positive reference voltage and said second plate to a second switching node; and

said switching device operable to select which of said first and second switching nodes are connected to said summing node in accordance with the state of the digital input data stream.

7. The data conversion system of claim 6, wherein said first and second switched capacitors are of substantially the same value.

8. The data conversion system of claim 6, wherein said negative reference voltage comprises ground.

9. The data conversion system of claim 6, wherein said output capacitance device comprises an output capacitor having associated therewith first and second plates, with first and second switching devices associated with said first and second plates, respectively, said first and second switching devices operable during said first time period to connect said associated first and second plates to said negative reference voltage and, during said second time period, to connect said respective first and second plates to said summing node and said output node, respectively.

10. A method for converting a one-bit digital input data stream having first and second logic states to a continuous time analog output signal, comprising the steps of:

providing a summing node and an output node;

disposing an integration stage between the summing node and the output node, the integration stage operable to integrate charge supplied to the summing node across a feedback capacitor disposed between the summing and output nodes to provide an integrated output signal on the output node;

adding a first predetermined amount of charge to the summing node during a first time period in the presence of the first logic state of the digital input data stream;

extracting a predetermined amount of charge from the summing node during the first time period and in the presence of a second logic state of the digital input signal; and

disposing an output capacitor across the feedback capacitor during a second time period subsequent to the first time period to distribute the charge in the feedback capacitor across the output capacitor and the feedback capacitor.

11. The method of claim 10, wherein the first and second predetermined amount of charges are substantially equal.

12. The method of claim 10, wherein the step of adding the first predetermined amount of charge comprises:

charging a first switching capacitor having first and second plates to a first voltage across the first and second plates with the first plate disposed at the higher voltage during the second time period; and

connecting the first plate of the first switched capacitor to a negative reference voltage and the second plate of the first switched capacitor to the summing node during the first time period and during the presence of the first logic state of the digital input data stream.

13. The method of claim 12, wherein the step of extracting the second predetermined amount of charge from the summing node during the first time period comprises:

providing a second switching capacitor having first and second plates;

during the second time period, connecting the first and second plates of the second switching capacitor to the negative reference voltage; and

during the first time period, connecting the first plate of the capacitor to the positive reference voltage and the second plate of the capacitor to the summing node during the presence of the second logic state of the digital input data stream.

14. A digital-to-analog converter for receiving a one-bit digital input data stream having first and second states and outputting a continuous time differential analog signal, comprising:

an integration stage having a differential amplifier with a positive summing input node, a positive output node, a negative summing input node, and a negative output node, and first and second feedback capacitors disposed between said positive and negative summing input nodes and said positive and negative output nodes;

positive and negative input charging devices, each of said positive and negative input charging devices operating in first and second modes, in said first mode said input charging devices operable to input a finite amount of charge to said positive and negative summing nodes and, in said second mode, operable to extract a finite amount of charge from said positive and negative summing nodes;

first and second output capacitance devices associated with said first and second feedback capacitors, respectively, for disposing respective first and second output capacitances across said first and second feedback capacitors to distribute the charge on said first and second feedback capacitors between said respective first and second feedback capacitors and said respective output capacitances; and

a switching device for controlling said positive and negative input charging devices to operate in said first mode for the first state of the input digital data stream and to operate in said second mode for the second state of the digital input data stream, said switching device operable to connect said positive and negative input charging devices to said positive and negative summing input nodes during a first time period to selectively add charge thereto or selectively subtract charge therefrom and connecting said first and second output capacitances across said respective first and second feedback capacitors during a second and subsequent time period.