Multiple serial-access memory
First Claim
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1. A serial access memory fabricated as a single integrated circuit, comprising:
- a plurality of memory cell arrays for storing data;
a like plurality of serial output ports coupled for serial output of data from respective memory cell arrays;
at least one serial input port coupled for input of serial data to one of said memory cell arrays; and
at least one transfer circuit coupled to transfer data from one of said memory cell arrays to another of said memory cell arrays.
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Abstract
A serial access memory consists of two or more memory cell arrays fabricated as a single integrated circuit. A serial input port is provided for input of data to one of the memory cell arrays. Separate serial output ports are provided for output of data from each of the memory cell arrays. Data are transferred among the memory cell arrays in parallel form by one or more internal transfer circuits.
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Citations
59 Claims
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1. A serial access memory fabricated as a single integrated circuit, comprising:
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a plurality of memory cell arrays for storing data; a like plurality of serial output ports coupled for serial output of data from respective memory cell arrays; at least one serial input port coupled for input of serial data to one of said memory cell arrays; and at least one transfer circuit coupled to transfer data from one of said memory cell arrays to another of said memory cell arrays. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A serial access memory fabricated as a single integrated circuit, comprising:
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a plurality of memory cell arrays for storing data, said memory cell arrays being arranged in a series from a first memory cell array to a last memory cell array, each memory cell array except said last memory cell array being followed by a respective next memory cell array in said series; a like plurality of serial output ports coupled for serial output of data transferred out of corresponding memory cell arrays; a serial input port coupled to input serial data for transfer into said first memory cell array; and for each memory cell array except the last memory cell array in said series, a corresponding transfer circuit coupled to transfer data from that memory cell array to the next memory cell array in said series. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
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56. A method of storing data in an integrated circuit having a series of at least two memory cell arrays and a corresponding series of at least two output registers, and reading the stored data, comprising the steps of:
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(a) writing serial data into an input register in said integrated circuit; (b) transferring data in parallel from said input register to a first memory cell array in said series of memory cell arrays; (c) transferring data in parallel between each pair of adjacent memory cell arrays in said series of memory cell arrays, starting from said first memory cell array; (d) transferring data in parallel from each memory cell array in said series to a corresponding output register in said series of output registers; and (e) reading data serially from said output registers. - View Dependent Claims (57, 58, 59)
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Specification