Multiple serial-access memory

• US 5,377,154 A
• Filed: 01/28/1993
• Issued: 12/27/1994
• Est. Priority Date: 01/31/1992
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Takasugi, Atsushi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/010,645
• Time in Patent Office: 698 Days
• Field of Search: 365/221, 365/230.09, 365/230.01, 365/233, 365/230.05, 365/189.01, 365/189.04
• US Class Current: 365/221
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

A serial access memory consists of two or more memory cell arrays fabricated as a single integrated circuit. A serial input port is provided for input of data to one of the memory cell arrays. Separate serial output ports are provided for output of data from each of the memory cell arrays. Data are transferred among the memory cell arrays in parallel form by one or more internal transfer circuits.

Claims

1. A serial access memory fabricated as a single integrated circuit, comprising:

a plurality of memory cell arrays for storing data;

a like plurality of serial output ports coupled for serial output of data from respective memory cell arrays;

at least one serial input port coupled for input of serial data to one of said memory cell arrays; and

at least one transfer circuit coupled to transfer data from one of said memory cell arrays to another of said memory cell arrays.

2. The memory of claim 1, wherein said transfer circuit transfers data in parallel form.

3. The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding read enable signal to which said serial output port responds by:

outputting successive serial data while said read enable signal is active; and

continuing to output a last data of the successive serial data that is output before said enable signal is changed from active to inactive, while said read enable signal is inactive.

4. The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding output enable signal to which said serial output port responds by:

outputting successive serial data while said output enable signal is active; and

going to a high-impedance state while said output enable signal is inactive.

5. The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding read enable signal and a corresponding output enable signal, to which said serial output port responds by:

outputting successive serial data while said read enable signal and said output enable signal are both active;

continuing to output a last data of the successive serial data that is output before said enable signal is changed from active to inactive, while said read enable signal is inactive and said output enable signal is active; and

going to a high-impedance state while said output enable signal is inactive.

6. The memory of claim 1, wherein said memory receives a chip enable signal and responds by disabling serial input at said serial input port and serial output at all of said serial output ports while said chip enable signal is inactive.

7. The memory of claim 1, wherein said memory receives a clock signal and receives data at said input port in synchronization with said clock signal.

8. The memory of claim 7, wherein said memory outputs data at all of said output ports in synchronization with said clock signal.

9. The memory of claim 1, wherein said memory receives a read clock signal and outputs data from all of said output ports in synchronization with read clock signal.

10. The memory of claim 1, wherein said memory receives a plurality of read clock signals comprising, for each of said output ports, a corresponding read clock signal, and outputs data from each of said output ports in synchronization with the corresponding read clock signal.

11. A serial access memory fabricated as a single integrated circuit, comprising:

a plurality of memory cell arrays for storing data, said memory cell arrays being arranged in a series from a first memory cell array to a last memory cell array, each memory cell array except said last memory cell array being followed by a respective next memory cell array in said series;

a like plurality of serial output ports coupled for serial output of data transferred out of corresponding memory cell arrays;

a serial input port coupled to input serial data for transfer into said first memory cell array; and

for each memory cell array except the last memory cell array in said series, a corresponding transfer circuit coupled to transfer data from that memory cell array to the next memory cell array in said series.

12. The memory of claim 11, wherein said memory receives, corresponding to said plurality of memory cell arrays, a like plurality of row address strobe signals and a like plurality of read transfer signals and a like plurality of read transfer signals so that each row address signal has a corresponding read transfer signal and a corresponding memory cell array, and when a row address strobe signal is active said memory responds by:

transferring data into the corresponding memory cell array if the corresponding read transfer signal is inactive; and

transferring data out of the corresponding memory cell array if the corresponding read transfer signal is active.

13. The memory of claim 11, wherein said memory receives a row address strobe signal and, corresponding to said plurality of memory cell arrays, a like plurality of read transfer signals, so that each memory cell array has a corresponding read transfer signal, and when said row address strobe signal is active said memory responds by:

transferring data into each memory cell array for which the corresponding read transfer signal is inactive; and

transferring data out of each memory cell array for which the corresponding read transfer signal is active.

14. The memory of claim 11, wherein each of said memory cell arrays comprises a matrix of memory cells and each memory cell is identified by an X-address and a Y-address.

15. The memory of claim 14, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of X-addressing circuits, each X-addressing circuit being coupled to a corresponding memory cell array and selecting memory cells therein according to their X-addresses.

16. The memory of claim 15, wherein each transfer circuit simultaneously transfers data obtained from all memory cells selected by the X-addressing circuit of the corresponding memory cell array to memory cells selected by the X-addressing circuit of the next memory cell array.

17. The memory of claim 15, further comprising, for said first memory cell array:

an input register having storage elements corresponding to Y-addresses of said first memory cell array, coupled to receive data in serial form from said serial input port, temporarily store the data received, and provide the same data in parallel form to memory cells selected by the X-addressing circuit of said first memory cell array; and

a write Y-addressing circuit for receiving Y-address signals and selecting corresponding storage elements in said input register for storing said data.

18. The memory of claim 17, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of output registers, each output register being coupled to a corresponding memory cell array, for receiving data in parallel form from memory cells selected by said X-addressing circuits, temporarily storing the data received, and providing the same data in serial form to corresponding serial output ports.

19. The memory of claim 18, wherein each memory cell array has pair of complementary bit lines, each pair of complementary bit lines being identified by a Y-address and coupled to memory cells having the same Y-address, and each said output register separately comprises a plurality of flip-flops coupled to said pairs of complementary bit lines in the corresponding memory cell array.

20. The memory of claim 19, wherein for each memory cell array except that the last memory cell array in said series, the corresponding transfer circuit comprises pairs of transistors coupling said flip-flops in the corresponding output register to corresponding pairs of bit lines in the next memory cell array, thereby enabling data to be transferred from said memory cell array to said corresponding output register and to the next memory cell array simultaneously.

21. The memory of claim 18, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of read Y-addressing circuits, each read Y-addressing circuit being coupled to a corresponding output register for selection of data stored therein to be provided to corresponding serial output ports.

22. The memory of claim 21, further comprising a write Y-address generator for generating Y-addresses and providing same to said write Y-addressing circuit.

23. The memory of claim 22, wherein said write Y-address generator also supplies Y-addresses to the read Y-addressing circuits of all of said memory cell arrays.

24. The memory of claim 22, wherein said write Y-address generator latches external Y-address signals.

25. The memory of claim 22, wherein said write Y-address generator comprises a resettable counter.

26. The memory of claim 25, wherein the resettable counter of said write Y-address generator is reset to zero when data are transferred into said first memory cell array.

27. The memory of claim 22, further comprising a read Y-address generator for generating a Y-addresses and providing same to the read Y-addressing circuits of all of said memory cell arrays.

28. The memory of claim 27, wherein said read Y-address generator latches external Y-address signals.

29. The memory of claim 27 wherein said read Y-address generator comprises a resettable counter.

30. The memory of claim 29, wherein the resettable counter of said read Y-address generator is reset to zero when data are transferred out of said first memory cell array.

31. The memory of claim 21, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of read Y-address generators for generating Y-addresses and providing same to the read Y-addressing circuits of respective memory cell arrays.

32. The memory of claim 31, wherein each of said read Y-address generators separately latches external Y-address signals.

33. The memory of claim 31, wherein each of said read Y-address generators separately comprises a resettable counter.

34. The memory of claim 33, wherein the resettable counter of each of said read Y-address generators is reset to zero when data are transferred out of the corresponding memory cell array.

35. The memory of claim 15, further comprising an X-address generator for latching external X-address signals and providing same to the X-addressing circuits of all of said memory cell arrays.

36. The memory of claim 15, further comprising, corresponding to the plurality of memory cell arrays, a like plurality of X-address generators arranged in a series from a first X-address generator to a last X-address generator, wherein each X-address generator has a corresponding memory cell array and provides X-addresses to the X-addressing circuit of the corresponding memory cell array.

37. The memory of claim 36, wherein each of said X-address generators separately latches external X-address signals.

38. The memory of claim 36, wherein each of said X-address generators separately comprises a write counter that generates X-addresses for use when data are transferred into the corresponding memory cell array.

39. The memory of claim 38, wherein said memory receives a plurality of initializing signals for initializing said X-address generators.

40. The memory of claim 39, wherein said first X-address generator also comprises a delay line for temporarily storing the X-addresses generated by the write counter of said first X-address generator, thereby permitting initialization of the write counter in said first X-address generator to precede input of corresponding data at said input port.

41. The memory of claim 39, wherein the write counter in said fist X-address generator is incremented when time data are transferred into said first memory cell array.

42. The memory of claim 39 wherein, when data are transferred out of each memory cell array except the last memory cell array, the write counter in the X-address generator of the next memory cell array is incremented.

43. The memory of claim 39, wherein the write counter in each of said X-address generators is initialized to zero.

44. The memory of claim 39, wherein the write counter in each of said X-address generators is initialized according to an external X-address signal.

45. The memory of claim 39, wherein said first X-address generator also comprises a read counter that generates X-addresses for use when data are transferred out of all of said memory cell arrays.

46. The memory of claim 45, wherein the read counter of said first X-address generator is incremented each time data are transferred out of said first memory cell array.

47. The memory of claim 45, wherein said plurality of initializing signals comprises a separate initializing signal for initializing the write counter in each of said X-address generators the read counter in said first X-address generator being initialized when the write counter in the next X-address generator is initialized.

48. The memory of claim 47, wherein the read counter in said first X-address generator is initialized to zero.

49. The memory of claim 47, wherein the read counter in said first X-address generator is initialized according to an external X-address signal.

50. The memory of claim 39, wherein each of said X-address generators separately comprises a read-address counter that generates X-addresses for use when data are transferred out of the corresponding memory cell array.

51. The memory of claim 50, wherein the read X-address counter in each of said X-address generators is incremented each time data are transferred out of the corresponding memory cell array.

52. The memory of claim 50, wherein the read counter in each of said address generators is initialized to zero.

53. The memory of claim 50, wherein the read counter in each of said X-address generators is initialized according to an external X-address signal.

54. The memory of claim 50, wherein the write counter in each of said X-address generators except the first X-address generator is initialized to zero, and the read counter in each of said X-address generators except the last X-address generator is initialized to zero.

55. The memory of claim 50, wherein said plurality of initializing signals comprises:

a first initializing signal for initializing the write counter of said first X-address generator;

a last initializing signal for initializing the read counter of said last X-address generator; and

for each X-address generator except the last X-address generator, a corresponding initializing signal for initializing both the read counter in said X-address generator and the write counter in the next X-address generator.

56. A method of storing data in an integrated circuit having a series of at least two memory cell arrays and a corresponding series of at least two output registers, and reading the stored data, comprising the steps of:

(a) writing serial data into an input register in said integrated circuit;

(b) transferring data in parallel from said input register to a first memory cell array in said series of memory cell arrays;

(c) transferring data in parallel between each pair of adjacent memory cell arrays in said series of memory cell arrays, starting from said first memory cell array;

(d) transferring data in parallel from each memory cell array in said series to a corresponding output register in said series of output registers; and

(e) reading data serially from said output registers.

57. The method of claim 56, wherein said steps (c) and (d) are performed simultaneously, with transfer of identical data in both steps (c) and (d).

58. The method of claim 56, wherein said steps (a) and (e) are performed simultaneously.

59. The method of claim 56, comprising the further step of:

(f) generating, by means of counters in said integrated circuit, addresses in said memory cell arrays for use in transferring data in said steps (c) and (d).