Non-blocking crossbar permutation engine with constant routing latency

• US 5,377,182 A
• Filed: 08/18/1993
• Issued: 12/27/1994
• Est. Priority Date: 08/18/1993
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Inventors: Monacos, Steve P.
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US08/111,318
• Time in Patent Office: 496 Days
• Field of Search: 370/16, 370/54, 370/56, 370/58.1, 370/58.2, 370/58.3, 370/60, 370/60.1, 370/63, 370/65, 370/65.5, 370/94.1, 340/825.02, 340/825.03, 340/826, 340/827, 340/825.79, 340/825.8, 379/219, 379/220, 379/221, 379/268, 379/269, 379/271, 379/272, 379/273, 379/291, 379/334, 379/335, 359/109, 359/115, 359/117, 359/124, 359/127, 359/128, 359/135, 359/140
• US Class Current: 370/219
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 2011/0011 using wavelength conversion
• CPC Class Codes: H04Q 2011/0015 using splitting combining
• CPC Class Codes: H04Q 2011/002 using optical delay lines or optical buffers or optical recirculation
• CPC Class Codes: H04Q 2011/0024 using space switching
• CPC Class Codes: H04Q 2011/0052 Interconnection of switches

Abstract

The invention is embodied in an N×N crossbar for routing packets from a set of N input ports to a set of N output ports, each packet having a header identifying one of the output ports as its destination, including a plurality of individual links which carry individual packets, each link having a link input end and a link output end, a plurality of switches, each of the switches having at least top and bottom switch inputs connected to a corresponding pair of the link output ends and top and bottom switch outputs connected to a corresponding pair of link input ends, whereby each switch is connected to four different links, each of the switches having an exchange state which routes packets from the top and bottom switch inputs to the bottom and top switch outputs, respectively, and a bypass state which routes packets from the top and bottom switch inputs to the top and bottom switch outputs, respectively, a plurality of individual controller devices governing respective ones of the switches for sensing from a header of a packet at each switch input the identity of the destination output port of the packet and selecting one of the exchange and bypass states in accordance with the identity of the destination output port and in accordance with the location of the corresponding switch relative to the destination output port.

Claims

1. An N×

N crossbar for routing packets from a set of N input ports to a set of N output ports, each packet having a header identifying one of said output ports as its destination, comprising;

a plurality of individual links which carry individual packets, each link having a link input end and a link output end;

a plurality of switches, each of said switches having at least top and bottom switch inputs connected to a corresponding pair of said link output ends and top and bottom switch outputs connected to a corresponding pair of link input ends, wherein each switch is connected to four different links and wherein different outputs of each one of at least some of said switches are connected through respective links to inputs of different switches, each of said switches having an exchange state which routes packets from said top and bottom switch inputs to said bottom and top switch outputs, respectively, and a bypass state which routes packets from said top and bottom switch inputs to said top and bottom switch outputs, respectively; and

a plurality of individual controller means governing respective ones of said switches for sensing from a header of a packet at each switch input the identity of the destination output port of the packet and selecting one of said exchange and bypass states as a function of the identity of said destination output port and as a function of the location of the corresponding switch relative to said destination output port.

2. The crossbar of claim 1 wherein said plurality of individual links are connected between nearest neighbors of said switches, and wherein none of said links overlaps any others of said links.

3. The crossbar of claim 1 wherein said controller means comprises means for selecting an exchange state whenever the packets at the switch inputs would not be precluded from reaching their destination output ports by setting the switch to said exchange state.

4. The crossbar of claim 3 wherein said N input ports are those of said link input ends not connected to switches and constituting one end of said crossbar and said N output ports are those of said link output ends not connected to switches and constituting another end of said crossbar.

5. The crossbar of claim 4 wherein said controller means comprises:

means for associating said output ports with a set of consecutive numbers;

means for associating each of said links with the number of the output port in the direct path thereof as a link label;

means for determining a first value equal to the absolute value of the difference between the link label corresponding to the top switch output and the number of the destination output port of a particular packet at an input port of the switch, and a second value equal to the absolute value of the difference between the link label corresponding to the bottom switch output and said number of said destination output port of said particular packet;

first routing means for routing said particular packet to said top switch output if said first value is less than said second value and for routing said particular packet to said bottom switch output if said second value is less than said first value.

6. The crossbar of claim 5 wherein said controller means further comprises:

second routing means for forbidding a switch bypass state if the packet is at the bottom switch input and said destination number is greater than the link label corresponding to the bottom switch output and for forbidding a switch bypass state if the packet is at the top switch input and said destination number is less than the link label corresponding to the top switch input.

7. The crossbar of claim 6 wherein said means for selecting further comprises means for forbidding the exchange state of said switch if packets at said top and bottom switch inputs cause said first and second routing means to select the same switch output for both packets contemporaneously.

8. The crossbar of claim 7 wherein said controller means comprises means for comparing said destination output port number of a packet at each of said top and bottom switch inputs with a predetermined set of numbers prescribed for the particular switch and for generating an up signal upon a match and a down signal otherwise for each of said packets and means for selecting said exchange state unless there are two up signals or two down signals.

9. The crossbar of claim 8 further comprising means for holding each of said switches in one of said exchange and bypass states selected by the controller means thereof while a packet traverses said crossbar.

10. The crossbar of claim 1 wherein said links are characterized by a delay along the lengths thereof and wherein said switches are characterized by a delay therethrough.

11. The crossbar of claim 10 wherein said plurality of links form a planar mesh having top and bottom edges, said crossbar further comprising delay elements each having the same delay as said switches, each delay element connecting a link input end to a link output end at a corresponding edge of said mesh.

12. The crossbar of claim 11 wherein each of said links lies along a diagonal path and wherein said switches and said delay elements lie at points of intersection of different diagonal paths.

13. The crossbar of claim 1 wherein said plurality of links correspond to a cylindrical wrap-around topology.

14. A non-blocking crossbar, comprising at least a pair of cascaded permutation engines, each of said permutation engines comprising an N×

N crossbar for routing packets from a set of N input ports to a set of N output ports, each packet having a header identifying one of said output ports as its destination, comprising;

a plurality of individual links which carry individual packets, each link having a link input end and a link output end;

a plurality of switches, each of said switches having at least top and bottom switch inputs connected to a corresponding pair of said link output ends and top and bottom switch outputs connected to a corresponding pair of link input ends, wherein each switch is connected to four different links and wherein different outputs of each one of at least some of said switches are connected through respective links to inputs of different switches, each of said switches having an exchange state which routes packets from said top and bottom switch inputs to said bottom and top switch outputs, respectively, and a bypass state which routes packets from said top and bottom switch inputs to said top and bottom switch outputs, respectively; and

a plurality of individual controller means governing respective ones of said switches for sensing from a header of a packet at each switch input the identity of the destination output port of the packet and selecting one of said exchange and bypass states as a function of the identity of said destination output port and as a function of the location of the corresponding switch relative to said destination output port, wherein the output ports of one of said permutation engines is connected to respective ones of the input ports of the other of said permutation engines.

15. The non-blocking crossbar of claim 14 wherein said plurality of individual links are connected between nearest neighbors of said switches, and wherein none of said links overlaps any others of said links.

16. The non-blocking crossbar of claim 14 wherein said controller means comprises means for selecting an exchange state whenever the packets at the switch inputs would not be precluded from reaching their destination output ports by setting the switch to said exchange state.

17. The non-blocking crossbar of claim 16 wherein said N input ports are those of said link input ends not connected to switches and constituting one end of said crossbar and said N output ports are those of said link output ends not connected to switches and constituting another end of said crossbar.

18. The non-blocking crossbar of claim 17 wherein said controller means comprises:

means for associating said output ports with a set of consecutive numbers;

means for associating each of said links with the number of the output port in the direct path thereof as a link label;

means for determining a first value equal to the absolute value of the difference between the link label corresponding to the top switch output and the number of the destination output port of a particular packet at an input port of the switch, and a second value equal to the absolute value of the difference between the link label corresponding to the bottom switch output and said number of said destination output port of said particular packet;

first routing means for routing said particular packet to said top switch output if said first value is less than said second value and for routing said particular packet to said bottom switch output if said second value is less than said first value.

19. The non-blocking crossbar of claim 18 wherein one of said permutation engines is inverted with respect to the other wherein said top and bottom switch inputs of one are reversed relative to the other and the numbering of said output ports is reversed relative to the other.

20. The non-blocking crossbar of claim 18 wherein said controller means further comprises:

second routing means for forbidding a switch bypass state if the packet is at the bottom switch input and said destination number is greater than the link label corresponding to the bottom switch output and for forbidding a switch bypass state if the packet is at the top switch input and said destination number is less than the link label corresponding to the top switch input.

21. The non-blocking crossbar of claim 20 wherein said controller means further comprises means for forbidding the exchange state of said switch if packets at said top and bottom switch inputs cause said first and second routing means to select the same switch output for both packets contemporaneously.

22. The non-blocking crossbar of claim 21 wherein said controller means comprises means for comparing said destination output port number of a packet at each of said top and bottom switch inputs with a predetermined set of numbers prescribed for the particular switch and for generating an up signal upon a match and a down signal otherwise for each of said packets and means for selecting said exchange state unless there are two up signals or two down signals.

23. The crossbar of claim 22 further comprising means for holding each of said switches in one of said exchange and bypass states selected by the controller means thereof while a packet traverses said crossbar.

24. The non-blocking crossbar of claim 14 wherein said links are characterized by a uniform delay along the lengths thereof and wherein said switches are characterized by a uniform delay therethrough.

25. The non-blocking crossbar of claim 24 wherein said plurality of links form a planar mesh having top and bottom edges, said crossbar further comprising delay elements each having the same delay as said switches, each delay element connecting a link input end to a link output end at a corresponding edge of said mesh.

26. The non-blocking crossbar of claim 25 wherein each of said links lies along a diagonal path and wherein said switches and said delay elements lie at points of intersection of different diagonal paths.

27. The non-blocking crossbar of claim 14 wherein said links form a wrap-around topology.