Transitive closure based process for generating test vectors for VLSI circuit

• US 5,377,201 A
• Filed: 12/19/1991
• Issued: 12/27/1994
• Est. Priority Date: 06/18/1991
• Status: Expired due to Term

• Current Assignee: AT&T Corporation (AT&T, Inc.), NEC Corporation
• Original Assignee: AT&T Corporation (AT&T, Inc.), NEC Research Institute, Inc. (NEC Corporation)
• Inventors: Chakradhar, Srimat, Agrawal, Viswani
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/813,144
• Time in Patent Office: 1,104 Days
• Field of Search: 371/27, 371/23, 395/575
• US Class Current: 714/741
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation

Abstract

A process for generating a vector for testing a digital circuit for a given fault first creates a composite circuit including a fault-present version of the circuit and a fault-free version. An implication graph is developed for the composite circuit and its energy function is derived as a combination of binary and ternary terms. All signal states that are consistent with the circuit function minimize the energy function to zero value. The transitive closure is computed for the binary terms, and redundancies, contradictions, fixations, identification and exclusions are identified. By iteration of implication graphs and transitive closures together with arbitrarily assigned signal values all ternary terms of the energy function are converted to binary terms, after which transitive closure recomputes a set of literals that can be used to generate the desired test vector by a standard branch and bound procedure.

Claims

1. A method for testing a logic circuit that comprises generating a test vector consisting of a set of signal values for a detecting a given fault in the logic circuit, where decisions on signal values are directed by a transitive closure computation on an implication graph model of the circuit, the decisions made from the class including fixations, identifications, exclusions and contradictions comprising the steps of

(a) deriving a fault function version of the digital circuit and combining it with its fault free function version to form a composite function version of the digital circuit,

(b) deriving the energy function of the composite function version and separating it into binary and ternary terms,

(c) forming an implication graph of the binary terms of the energy function,

(d) computing the transitive closure of the implication graph,

(e) determining from the transitive closure any fixations, identifications, exclusions or contradictions and using any found to reduce some ternary terms of the energy function to new binary temps,

(f) forming a new implication graph by adding to the previous implication graph the new binary terms,

(g) computing a new transitive closure based on the new implication graph,

(h) repeating steps (e), (f) and (g) so long as it is possible to remove ternary terms from the energy function,

(i) if no ternary terms remain, deriving a list of literals,

(j) if ternary terms remain, fixing an unassigned signal to a particular value and repeating steps (c), (d), (e), (f), (g), (h) and (i) and determining any redundancies fixations, identifications, exclusions or contradictions so long as ternary terms are being eliminated, and then deriving a list of literals,

(k) if ternary terms remain, fixing the unassigned signal to the opposite value and repeating steps (c), (d), (e), (f), (g), (h) and (i)

(l) from the list of literals, deriving a test vector for the fault, converting the test vector into an electrical signal, and, applying the electrical signal as an input to the logic circuit for testing for the fault and detecting the output of the logic signal to discern existence of a fault.

2. The method of claim 1 in which the testing is for a set of particular faults and the method for generating a test vector for a particular fault is repeated for each fault to derive a set of test vectors for testing for the set of particular faults and each of the set of derived test vectors is applied to the circuit under test and the output detected for discerning the corresponding fault.

3. The method of providing a digital circuit that is to be free of specific faults comprising, manufacturing a batch of said digital circuits, testing the integrity of each digital circuit for any of the faults by applying to the circuit a set of test vectors, each test vector of the set being designed to discover a different one of the particular faults, each of the test vector having been derived by a process that comprises

(a) simulating a composite circuit that combines in parallel a version of the tested digital circuit that includes the particular fault with a version that is free of the particular fault,

(b) deriving the energy function of the composite circuit by combining the energy functions of its logic gates and separating it into binary and ternary terms,

(c) forming an implication graph of the binary terms of the energy function,

(d) computing the transitive closure of the implication graph,

(e) determining from the transitive closure any fixations, identifications, exclusions and contradictions and using any that are found to reduce ternary terms of the energy function to new binary terms,

(f) forming a new implication graph by adding to it the new binary terms,

(g) computing a new transitive closure based on the new implication graph,

(h) repeating steps (e), (f) and (g) so long as it is possible to remove ternary terms from the energy function,

(i) if ternary terms remain, fix an unassigned signal to a particular value and repeat the updating of she implication graph and the transitive closure, until all ternary terms are eliminated and there is derived a list of literals, and

(j) from the list of literals, deriving a test vector for the fault, applying in turn the test vectors of the set to each digital circuit of the batch, detecting each output of each digital circuit for discerning whether the tested digital circuit includes any of the particular faults.