Frequency synchronized bidirectional radio system

• US 5,377,232 A
• Filed: 01/09/1992
• Issued: 12/27/1994
• Est. Priority Date: 01/09/1992
• Status: Expired due to Term

• Current Assignee: Landis+Gyr Innovations Incorporated (Landis+Gyr Group AG)
• Original Assignee: CellNet Data Systems, Inc. (Landis+Gyr Group AG)
• Inventors: Davidov, Mircho A., Fulton, Forrest F.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US07/818,693
• Time in Patent Office: 1,083 Days
• Field of Search: 375/107, 375/120, 375/42, 375/39, 375/80, 375/109, 375/118, 375/81, 375/106, 455/51, 455/75, 455/76, 370/104.1, 370/100.1, 370/85.8, 370/95.2, 370/105.4, 370/110.1
• US Class Current: 375/354
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04B 7/2675 Frequency synchronisation
• CPC Class Codes: H04J 1/065 Synchronisation of carrier sources at the receiving station with the carrier source at the transmitting station
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier
• CPC Class Codes: H04L 27/3854 using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

A bidirectional radio system for low cost, high through-put accumulation of data from a large number of site units. The site units are connected to remote radio transceivers in radio communication with a plurality of base stations. Accurate frequency synchronization allows multiple carriers within a 12.5 kHz FCC bandwidth. Frequency synchronization is achieved at low cost by transmitting a high accuracy carrier and clock signal at a base station, and using receiving circuitry a remote stations to extract the base clock signal and base carrier frequency and a phase-lock loop to stabilize the remote station carriers. The reception circuitry at a remote station provides independent carrier frequency and clock rate recovery, a phase-lock loop at baseband, and a coarse clock rate recovery circuit coupled to a fine clock rate recovery circuit. Remote station responses are time domain multiplexed. A base station receiver can decode a very short remote station response by scaling the response with the phase and amplitude of an initial segment of the response. Spatial reuse of carrier frequencies further increases the rate of data through-put.

Claims

1. A bidirectional communication system comprising at least one communication cell having a base station and at least one remote station, in said cell said remote station receiving polling signals from said base station at a precise base clock rate on a precise base carrier frequency, in said cell said remote station transmitting response signals at a remote clock rate to said base station on a remote carrier frequency, said base clock rate being extracted at said remote station from said polling signals to generate said remote clock rate in synchronization with said base clock rate, said remote station calculating frequency error information relating to a difference in frequency between said precise base carrier frequency and said remote carrier frequency, and both said frequency error information and said remote clock rate being utilized in phase-lock loop circuitry in said remote station to stabilize said remote carrier frequency.

2. The communication system of claim 1 wherein an initial segment of a burst of data received by said base station from said remote station is used to scale a phase and an amplitude of a remainder of the burst.

3. The system of claim 1 or 2 wherein said polling signals are quadrature encoded and further comprising an apparatus for decoding in-phase and quadrature components of said polling signals at said remote station, said polling signals having a first component and a second component, said first component being an estimated in-phase component and said second component being an estimated quadrature component, said apparatus being comprised of:

a) a rotator, said rotator generating a first rotated component and a second rotated component from said first component and said second component in response to a rotation signal;

b) a phase detector, said phase detector detecting an amount of in-phase component and quadrature components in said first component and second component and generating a ramp control signal; and

c) a ramp estimator, said ramp estimator reading said ramp control signal and generating said rotation signal such that said first and second rotated components are substantially equivalent to the in-phase and quadrature components of said polling signal, and said ramp estimator generating said frequency error information.

4. The system of claim 3, further comprising:

a coarse clock estimator, said coarse clock estimator generating a sequence of coarse clock pulses from said first and second rotated components; and

a fine clock timing error estimator, said fine clock timing error estimator sampling said coarse clock pulses to produce remote clock timing error information from values of said first and second rotated components, said remote clock timing error information being utilized in phase-lock loop circuitry in said remote station to stabilize said remote clock rate.

5. The system of claim 4, further comprising:

an amplitude estimator, said amplitude estimator generating an amplitude estimate from a sum of squares of said first and second rotated components, and

first and second multipliers, said first and second multipliers scaling said first and second components, respectively, by an amount inversely related to said amplitude estimate.

6. The system of claim 1 or 2, further comprising an apparatus for extracting a clock signal from a signal having a first and a second rotated component, said apparatus comprising:

a coarse clock estimator, said coarse clock estimator generating a sequence of coarse clock pulses from said first and second rotated components; and

a fine clock timing error estimator, said fine clock timing error estimator sampling said coarse clock pulses to produce remote clock timing error information from values of said first and second rotated components, said timing error information being utilized in phase-lock loop circuitry in said remote station to stabilize said remote clock rate.

7. The system of claim 6 wherein said polling signals are quadrature encoded, and further comprising an apparatus for decoding in-phase and quadrature components of said polling signal at said remote station, said polling signal having a first component and a second component, said first component being an estimated in-phase component and said second component being an estimated quadrature component, said apparatus being comprised of:

a) a rotator, said rotator generating said first rotated component and said second rotated component from said first component and said second component in response to a rotation signal;

b) a phase detector, said phase detector detecting an amount of in-phase component and quadrature components in said first component and second component and generating a ramp control signal; and

c) a ramp estimator, said ramp estimator reading said ramp control signal and generating said rotation signal such that said first and second rotated components are substantially equivalent to the in-phase and quadrature components of said polling signal, and said ramp estimator generating base carrier frequency information.

8. The system of claim 7, further comprising:

an amplitude estimator, said amplitude estimator generating an amplitude estimate from a sum of squares of said first and second rotated components, and

first and second multipliers, said first and second multipliers scaling said first and second components, respectively, by an amount inversely related to said amplitude estimate.

9. A bidirectional radio communication system comprised of at least one communication cell, said cell having a base station and at least one remote station, said remote station receiving a polling signal at a precise base clock rate on a precise base carrier frequency from said base station, said remote station transmitting response signals at a remote clock rate to said base station on a remote carrier frequency, said remote station being comprised of:

a first frequency synthesizer generating said remote carrier frequency, said remote carrier frequency being stabilized by a first stabilization signal directed to said first synthesizer;

a first frequency heterodyne, said first heterodyne heterodyning said remote carrier frequency and polling signal received from said base station to generate an intermediate frequency signal;

a second frequency synthesizer generating an intermediate frequency sinusoid, said intermediate frequency sinusoid being stabilized by a second frequency stabilization signal;

a second frequency heterodyne, said second heterodyne heterodyning said intermediate frequency sinusoid and said intermediate frequency signal to generate a baseband signal;

a first recovery circuit, said first recovery circuit recovering carrier frequency error information from said baseband signal and generating said first frequency stabilization signal; and

a second recovery circuit, said second recovery circuit generating said second frequency stabilization signal from said baseband signal, and synchronizing said remote clock rate and said precise base clock rate.

10. An apparatus for decoding in-phase and quadrature components of a quadrature encoded signal, said quadrature encoded signal having a first component and a second component, said first component being an estimated in-phase component add raid second component being an estimated quadrature component, said apparatus being comprised of:

a) a rotator, said rotator generating a first rotated component and a second rotated component from said first component and said second component in response to a rotation signal;

b) a phase detector, said phase detector detecting an amount of in-phase component and quadrature components in said first component and said second component and generating a ramp control signal;

c) a ramp estimator, said ramp estimator reading said ramp control signal and generating said rotation signal such that said first and second rotated components are substantially equivalent to the in-phase and quadrature components of said quadrature encoded signal;

d) a coarse clock estimator, said coarse clock estimator generating a sequence of coarse clock pulses from said first and second rotated components; and

e) a fine clock timing error estimator sampling said coarse clock pulses to produce clock timing error information from values of said first and second rotated components, said timing error information being utilized in phase-lock loop circuitry to stabilize said clock pulses.

11. The apparatus of claim 10, further comprising:

an amplitude estimator generating an amplitude estimate from a sum of squares of said first and second rotated components, and

first and second multipliers, said first and second multipliers scaling said first and second components, respectively, by an amount inversely proportional to said amplitude estimate.

12. The apparatus of claim 11 wherein said coarse clock estimator generates said coarse clock pulses from a square of a sum of squares of said first and second rotated components.

13. An apparatus for extracting a clock timing error signal from a quadrature encoded signal, said quadrature encoded signal having a first rotated component and a second rotated component, said apparatus comprising:

a coarse clock estimator, said coarse clock estimator generating a sequence of coarse clock pulses from a square of sum of squares of said first and second rotated components; and

a fine clock timing error estimator, said coarse clock pulses being fed to said fine clock timing error estimator from said coarse clock estimator, said fine clock timing error estimator sampling said first and second rotated component at times corresponding to said coarse clock pulses to produce said clock timing error signal.

14. The apparatus of claim 13, further comprising a decoding apparatus for decoding in-phase and quadrature components of a quadrature encoded signal, said quadrature encoded signal having a first component and a second component, said first component being an estimated in-phase component and said second component being an estimated quadrature component, said decoding apparatus being comprised of:

a) a rotator, said rotator generating said first rotated component and said second rotated component from said first component and said second component in response to a rotation signal;

b) a phase detector, said phase detector detecting an amount of in-phase component and quadrature components in said first component and said second component and generating a ramp control signal; and

c) a ramp estimator, said ramp estimator reading said ramp control signal and generating said rotation signal such that said first and second rotated components are substantially equivalent to the in-phase and quadrature components of said quadrature encoded signal.

15. The apparatus of claim 14, further comprising:

an amplitude estimator generating an amplitude estimate from a sum of squares of said first and second rotated components, and

first and second multipliers, said first and second multipliers scaling said first and second components, respectively, by an amount inversely proportional to said amplitude estimate.

16. The apparatus of claim 16 wherein said coarse clock estimator generates said coarse clock pulses from a square of a sum of squares of said first and second rotated components.

17. A method of decoding a short burst of data from quadrature demodulated components of a signal comprising the steps of:

calculating an amplitude and phase of a predetermined reference segment of said short burst to generate a scaling amplitude and a scaling phase, using said scaling amplitude to scale an amplitude of a remainder segment of said short burst and said scaling phase to scale a phase of a remainder segment of said short burst to provide a scaled remainder signal, and demodulating data from said scaled remainder signal.