Converting a central arbiter to a slave arbiter for interconnected systems

• US 5,377,331 A
• Filed: 03/26/1992
• Issued: 12/27/1994
• Est. Priority Date: 03/26/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Peterson, James C., Drerup, Bernard C.
• Primary Examiner(s): CHUN, DEBRA
• Application Number:
  US07/857,880
• Time in Patent Office: 1,006 Days
• Field of Search: 395/325, 395/275, 395/725
• US Class Current: 710/113
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

A method and apparatus are disclosed for allowing at least one computer subsystem, having a central arbiter, to be interconnected with a host system also including a central arbiter. Conversion logic is added to each computer subsystem desired to be interconnected to the host. The conversion logic is positioned between the arbitration buses of the host system and the subsystem and includes two requesting arbiters, one of which arbitrates for the host system arbitration bus, and the other which arbitrates for the subsystem arbitration bus. At the default state, the conversion logic has successfully arbitrated for, and is maintaining control of the subsystem bus. After a request from a subsystem device for access to the host bus, the conversion logic arbitrates for control of the host bus. When control of the host bus is awarded to the conversion logic, control of the subsystem bus is released and the requesting subsystem device can transfer data between the subsystem and host.

Claims

1. A method of transferring data between a host computer system having a host system bus and at least one interconnected computer subsystem having a subsystem bus, comprising:

maintaining control of said subsystem bus by a conversion logic device connected intermediate said host bus and said subsystem bus to prevent a busmaster device, connected to said subsystem bus, from transferring data on said host bus;

requesting access to said host system bus, by a requesting busmaster device connected to said subsystem bus;

in response to said request for access, arbitrating by said conversion logic device, for control of said host system bus to prevent said host computer system from prematurely transferring data onto said host bus;

subsequent to obtaining control of said host system bus, releasing control of said subsystem bus by said conversion logic device such that said requesting busmaster device can gain control of said subsystem bus; and

transferring data between said busmaster device on said subsystem bus and said host system bus when said busmaster device controls said subsystem bus and said conversion logic device controls said host bus.

2. A method according to claim 1 wherein said step of arbitrating for control of said subsystem bus comprises the steps of:

arbitrating, by said control logic device, for control of said subsystem bus when said computer subsystem is initialized;

maintaining a default state wherein access to said subsystem is controlled by said conversion logic.

3. A method according to claim 2 wherein said step of arbitrating for control of said host system bus comprises the steps of:

arbitrating for control of said host system bus upon receipt of a request initiated by said busmaster device;

maintaining control of said host system bus until said transfer of data is complete; and

relinquishing control of said host system bus to said default state, wherein said host computer system controls said host bus, after control of said subsystem bus is regained.

4. A system for transferring data between a host computer system having a host system bus with at least one host busmaster device connected thereto, and at least one interconnected computer subsystem having at least one subsystem bus with at least one busmaster device connected thereto, comprising:

means, in said at least one busmaster device, for requesting access to said host system bus;

conversion logic means, connected intermediate said host bus and said subsystem bus, comprising;

means for maintaining control of said subsystem bus to prevent said at least one busmaster device from prematurely transferring data onto said host bus;

means for arbitrating for control of said host system bus, in response to said request for access, to prevent said host computer system from transferring data onto said host bus; and

means for releasing control of said subsystem bus, subsequent to obtaining control of said host system bus, such that said requesting busmaster device can gain control of said subsystem bus; and

means for transferring data between said busmaster device on said subsystem bus and said host system bus when said subsystem busmaster device controls said subsystem bus and said conversion logic controls said host bus.

5. A system according to claim 4 wherein said conversion logic means comprises:

a subsystem arbitration control circuit for communicating with busmaster devices interconnected to said subsystem bus;

a subsystem arbiter in communication with said subsystem arbitration control circuit and interconnected to said subsystem bus for arbitrating for control of said subsystem bus;

a host arbitration control circuit for communicating with busmaster devices interconnected to said host system bus; and

a host arbiter, in communication with said host and subsystem arbitration control circuits and interconnected to said host bus, for arbitrating for control of said host system bus.

6. A system according to claim 5 wherein said conversion logic means further comprises:

means for comparing a priority value of one of said host busmaster devices with a list of priority values corresponding to said subsystem busmaster devices; and

means for outputting said priority value to said subsystem arbiter when said host busmaster device priority value and one of said subsystem devices priority values match, wherein said subsystem arbiter uses said priority value when arbitrating for control of said subsystem bus.

7. A system according to claim 6 wherein said subsystem arbitration control circuit comprises means for requesting said host arbitration control circuit to acquire control of said host system bus.

8. A system according to claim 7 wherein said host arbitration control circuit comprises means for indicating to said subsystem arbitration control circuit that control of said host system bus has been acquired.

9. A system according to claim 6 wherein said means for comparing includes a look up table for storing said subsystem busmaster priority values to be compared with said host busmaster device priority value.