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Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency

  • US 5,377,338 A
  • Filed: 10/12/1993
  • Issued: 12/27/1994
  • Est. Priority Date: 10/12/1993
  • Status: Expired due to Term
First Claim
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1. A data processing system having a central processor (CP), a memory, an address bus coupled to said CP having signal lines for conveying memory addresses that are generated by said CP, and a data bus coupled to said CP for transferring data to and from said CP for memory read and memory write operations, respectively, said system further comprising:

  • address buffer means connected within said address bus between said CP and said memory for receiving and buffering memory addresses that are generated by said CP, said address buffer means comprising,a plurality of registers each having a width sufficient for storing a first portion of a memory address received from said CP during a CP write to memory operation, said plurality of registers including a first address register for storing a first portion of a first memory address received from said CP, and a second address register for storing said first portion of said first memory address received from said CP, said stored first portion of said first memory address being a content of said second address register; and

    comparator means having a first input that is coupled to an output of said second address register and a second input that is coupled to said address bus, for comparing said first portion of a second memory address that is received from said CP to said content of said second address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said CP is equal to said content of said second address register, and that (b) a write to memory operation for which said second memory address is generated can be combined with a write to memory operation for which said first memory address was generated;

    wherein said address buffer means further comprises a third address register for storing said first portion of said second memory address received from said CP, said third address register storing said first portion of said second memory address only when said output of said comparator means has a second state for indicating that said first portion of said second memory address that is received from said CP is not equal to said content of said second address register;

    said data processing system further comprising,data buffer means connected within said data bus between said CP and said memory for receiving and buffering CP write data corresponding to said memory addresses that are generated by said CP, said data buffer means comprising,a first data register for storing CP write data corresponding to said first portion of said address stored within said first address register, and a second data register for storing CP write data corresponding to said first portion of said address stored within said third address register;

    wherein said first data register and said second data register each have a width of a plurality of bytes, and wherein said data buffer means further includes a first mark bit register for storing indications of which bytes of said first data register are written in to, and a second mark bit register for storing indications of which bytes of said second data register are written in to; and

    means, responsive to mark bit indications stored within said first and second mark bit registers, for selectively merging data from one of said first and second data registers with data read from a memory location that is specified by a corresponding one of said first and third address registers.

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