Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency

• US 5,377,338 A
• Filed: 10/12/1993
• Issued: 12/27/1994
• Est. Priority Date: 10/12/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Wang Laboratories Incorporated
• Inventors: Mann, Edward D., Olson, Stephen W., MacDonald, James B., Petersen, James W. Jr.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Maung, Zarni
• Application Number:
  US08/134,806
• Time in Patent Office: 441 Days
• Field of Search: 395/425, 395/375, 395/500, 364/239.7, 364/243.5, 364/239
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.

Claims

1. A data processing system having a central processor (CP), a memory, an address bus coupled to said CP having signal lines for conveying memory addresses that are generated by said CP, and a data bus coupled to said CP for transferring data to and from said CP for memory read and memory write operations, respectively, said system further comprising:

address buffer means connected within said address bus between said CP and said memory for receiving and buffering memory addresses that are generated by said CP, said address buffer means comprising,

a plurality of registers each having a width sufficient for storing a first portion of a memory address received from said CP during a CP write to memory operation, said plurality of registers including a first address register for storing a first portion of a first memory address received from said CP, and a second address register for storing said first portion of said first memory address received from said CP, said stored first portion of said first memory address being a content of said second address register; and

comparator means having a first input that is coupled to an output of said second address register and a second input that is coupled to said address bus, for comparing said first portion of a second memory address that is received from said CP to said content of said second address register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said CP is equal to said content of said second address register, and that (b) a write to memory operation for which said second memory address is generated can be combined with a write to memory operation for which said first memory address was generated;

wherein said address buffer means further comprises a third address register for storing said first portion of said second memory address received from said CP, said third address register storing said first portion of said second memory address only when said output of said comparator means has a second state for indicating that said first portion of said second memory address that is received from said CP is not equal to said content of said second address register;

said data processing system further comprising,

data buffer means connected within said data bus between said CP and said memory for receiving and buffering CP write data corresponding to said memory addresses that are generated by said CP, said data buffer means comprising,

a first data register for storing CP write data corresponding to said first portion of said address stored within said first address register, and a second data register for storing CP write data corresponding to said first portion of said address stored within said third address register;

wherein said first data register and said second data register each have a width of a plurality of bytes, and wherein said data buffer means further includes a first mark bit register for storing indications of which bytes of said first data register are written in to, and a second mark bit register for storing indications of which bytes of said second data register are written in to; and

means, responsive to mark bit indications stored within said first and second mark bit registers, for selectively merging data from one of said first and second data registers with data read from a memory location that is specified by a corresponding one of said first and third address registers.

2. A data processing system as set forth in claim 1 and further comprising:

means, responsive to a second state of said output of said comparator means, for generating a memory request; and

means, responsive to said generated memory request, for decoding said mark bit indications stored within one of said first and second mark bit registers and for controlling said memory in response to said decoded mark bit indications to selectively perform one of a memory read operation, a memory read-modify-write operation, and a memory write operation.

3. A data processing system having an Input/Output controller (IOC), a memory, an address bus coupled to said IOC having signal lines for conveying memory addresses that are generated by said IOC, and a data bus coupled to said IOC for transferring data to and from said IOC during memory read and write operations, respectively, said system further comprising;

address buffer means connected within said address bus between said IOC and said memory for buffering a plurality of memory addresses that are generated by said IOC, said address buffer means comprising,

a plurality of registers each having a width sufficient for storing a first portion of a memory address received from said IOC during an IOC write to memory operation, said plurality of registers including a first register for storing a first portion of a first memory address received from said IOC, and a second register for storing said first portion of said first memory address received from said IOC, said stored first portion of said first memory address being a content of said second register; and

comparator means having a first input that is coupled to an output of said second register and a second input that is coupled to said address bus, for comparing said first portion of a second memory address that is received from said IOC to said content of said second register, said comparator means having an output for indicating, when in a first state, that (a) said first portion of said second memory address that is received from said IOC is equal to said content of said second register, and that (b) a write to memory operation for which said second memory address is generated can be combined with a write to memory operation for which said first memory address was generated;

wherein said address buffer means further comprises a third register for storing said first portion of said second memory address received from said IOC, said third register storing said first portion of said second memory address only when said output of said comparator means has a second state for indicating that said first portion of said second memory address that is received from said IOC is not equal to said content of said second register;

said data processing system further comprising,

data buffer means connected within said data bus between said IOC and said memory for receiving and buffering IOC write data corresponding to said memory addresses that are generated by said IOC, said data buffer means comprising,

a first data register for storing IOC write data corresponding to said first portion of address stored within said first address register, and a second data register for storing IOC write data corresponding to said first portion of said address stored within said third address register;

wherein said first data register and said second data register each have a width of a plurality of bytes, and wherein said data buffer means further includes a first mark bit register for storing indications of which bytes of said first data register are written in to, and a second mark bit register for storing indications of which bytes of said second data register are written in to; and

means, responsive to mark bit indications stored within said first and second mark bit registers, for selectively merging data from one of said first and second data registers with data read from a memory location that is specified by a corresponding one of said first and third address registers.

4. A data processing system as set forth in claim 3 and further comprising:

means, responsive to a second state of said output of said comparator means, for generating a memory request; and

means, responsive to said generated memory request, for decoding said mark bit indications stored within one of said first and second mark bit registers and for controlling said memory in response to said decoded mark bit indications to selectively perform one of a memory read operation, a memory read-modify-write operation, and a memory write operation.

5. A method for writing data to a main memory from a central processor (CP), comprising the steps of:

generating a first write request with said CP, said first write request including a generated address provided on an address bus and data provided on a data bus;

storing external to said CP a first portion of said address from said address bus in a first register and in a second register while decoding, external to said CP, said first write request to determine which bytes of a multi-byte data word are to be written to said main memory;

buffering external to said CP, in response to said decoded write request, selected bytes within a first data register and an indication of said selected bytes within a first mark bit register;

generating, external to said CP, a first memory request to perform a memory write operation at a location specified in part by said first portion of said address stored within said first register; and

while waiting for a completion of said write operation that is performed in response to said first memory request, and further in response to a generation of a second write request by said CP,

storing external to said CP said first portion of said address, from said address bus, that is generated for said second write request in a third register and in said second register while decoding, external to said CP, said second write request to determine which bytes of said multi-byte data word are to be written to said main memory;

buffering external to said CP, in response to said decoded second write request, selected bytes within a second data register and an indication of said selected bytes within a second mark bit register;

generating, external to said CP, a second memory request to perform a memory write operation at a location specified in part by said first portion of said address stored within said third register; and

while waiting for a completion of said first memory request, and further in response to a generation of a third write request by said CP, comparing, external to said CP, said first portion of said address generated for said third write request with said first portion of said address stored in said second register, and, if said two first portions are found to be equal;

storing, external to said CP, said first portion of said address from said address bus in said third register and in said second register while decoding, external to said CP, said third write request to determine which bytes of said multi-byte data word are to be written to said main memory; and

buffering external to said CP, in response to said decoded third write request, selected bytes within said second data register and an indication of said selected bytes within said second mark bit register.

6. A method as set forth in claim 5, wherein if said step of comparing said first portion of said address generated for said third write request with said first portion of said address stored in said second register indicates that said two first portions are not equal, said method includes a step of halting said CP third write request until said completion of said first memory request.

7. A method as set forth in claim 5 and further including the steps of:

performing said memory write operation for said first write request as a write operation or as read/modify/write operation of said data stored in said first data register in accordance with said mark bits stored in said first mark bit register; and

performing said memory write operation for said second write request as a write operation or as read/modify/write operation of said data stored in said second data register in accordance with said mark bits stored in said second mark bit register.

8. A method as set forth in claim 5 wherein said first portion of a memory address has a number of bits specifying a minimum resolution of a double word of memory addresses, wherein a double word consists of eight bytes.

9. A method for writing data to a main memory from an Input/Output Controller (IOC), comprising the steps of:

generating a first write request with said IOC, said first write request including a generated address provided on an address bus and data provided on a data bus;

storing external to said IOC a first portion of said address from said address bus in a first register and in a second register while decoding, external to said IOC, said first write request to determine which bytes of a multi-byte data word are to be written to said main memory;

buffering external to said IOC, in response to said decoded write request, selected bytes within a first data register and an indication of said selected bytes within a first mark bit register;

in response to said generation of a second write request by said IOC,

comparing, external to said IOC, said first portion of said address generated for said second write request with said first portion of said address stored in said second register, and, if said two first portions are found to be equal;

storing, external to said IOC, said first portion of said address from said address bus in said first register and in said second register while decoding, external to said IOC, said second write request to determine which bytes of said multi-byte data word are to be written to said main memory; and

buffering, external to said IOC, in accordance with said decoded second write request, selected bytes within said first data register and an indication of said selected bytes within said first mark bit register;

if said step of comparing said first portion of said address generated for said second write request with said first portion of said address stored in said second register indicates that said two first portions are not equal, the method includes the further steps of;

generating, external to said IOC, a first memory request to perform a memory write operation at a location specified by said first portion of said address stored within said first register;

storing, external to said IOC, said first portion of said address from said address bus that is generated for said second write request in a third register and in said second register while decoding, external to said IOC, said second write request to determine which bytes of said multi-byte data word are to be written; and

buffering external to said IOC, in response to said decoded second write request, selected bytes within a second data register and an indication of said selected bytes within a second mark bit register;

in response to said generation of a third write request by said IOC,

comparing, external to said IOC, said first portion of said address generated for said third write request with said first portion of said address stored in said second register, and, if said two first portions are equal;

storing, external to said IOC, said first portion of said address from said address bus in said third register and in said second register while decoding, external to said IOC, said third write request to determine which bytes of said multi-byte data word are to be written; and

buffering external to said IOC, in response to said decoded third write request, selected bytes within said second data register and an indication of said selected bytes within said second mark bit register.

10. A method as set forth in claim 9, wherein if said step of comparing said first portion of said address generated for said third write request with said first portion of said address stored in said second register indicates that said two first portions are not equal, the method includes the steps of:

storing, external to said IOC, said first portion of said address from said address bus in said first register and in said second register while decoding, external to said IOC, said third write request to determine which bytes of said multi-byte data word are to be written;

buffering external to said IOC, in response to said decoded write request, selected bytes within said first data register and an indication of said selected bytes within said first mark bit register; and

generating a second memory request to perform a memory write operation at a location specified by said first portion of said address stored within said third register.

11. A method as set forth in claim 10 and further including the steps of:

performing said memory write operation for said first write request as a write operation or as read/modify/write operation of said data stored in said first data register in accordance with said mark bits stored in said first mark bit register; and

performing said memory write operation for said second write request as a write operation or as read/modify/write operation of said data stored in said second data register in accordance with said mark bits stored in said second mark bit register.

12. A method as set forth in claim 9 wherein said first portion of a memory address has a number of bits specifying a minimum resolution of a double word of memory addresses, wherein a double word consists of eight bytes.

13. A method for reading data from a main memory with an Input/Output Controller (IOC), comprising the steps of:

(a) generating a first read request with said IOC, said first read request including an address provided on an address bus;

(b) receiving, external to said IOC, said address from said address bus and aligning said received address so as to be on a main memory address boundary;

(c) storing, external to said IOC, said aligned address in a first register and in a second register;

(d) incrementing, external to said IOC, said aligned address to a next memory boundary and storing, external to said IOC, said incremented aligned address in a third register;

(e) generating, external to said IOC, a first memory request to perform a memory read operation at a location specified by said aligned address stored within said first register;

(f) at a completion of said memory read operation performed by said first memory request, buffering, external to said IOC, said read data in a first data register;

(g) generating, external to said IOC, a memory request to perform a memory read operation at a location specified by said incremented aligned address stored within said third register;

(h) at a completion of said memory read operation performed by said second memory request, buffering, external to said IOC, said read data in a second data register;

(i) generating a next read request with said IOC, said next read request including an address provided on said address bus;

(j) receiving, external to said IOC, said address from said address bus and aligning said received address to be on a next main memory address boundary;

(k) comparing, external to said IOC, said aligned address generated for said second read request with said aligned address stored in said second register, and, if said two aligned addresses are equal;

(l) returning data from said first data register to said IOC;

else, if said two aligned addresses are not equal,

(m) transferring said data stored within said second data register to said first data register;

(n) returning data from said first data register to said IOC;

(n) incrementing, external to said IOC, said aligned address generated for said next read request to a next memory boundary and storing said incremented aligned address in said third register, while storing said aligned address generated for said next read request in said second register;

(o) generating, external to said IOC, a next memory request to perform a memory read operation at a location specified by said incremented aligned address stored within said third register;

(p) at a completion of said memory read operation performed by said next memory request, buffering, external to said IOC, said read data in said second data register; and

(o) repeating steps (i) through (p) until said IOC terminates reading data from said main memory.

14. A method as set forth in claim 13 wherein said memory boundary is a quad-word boundary, wherein a quad-word consists of sixteen bytes.

15. A method as set forth in claim 13 wherein said method includes, for each of said steps of generating a memory request, the steps of:

decoding, external to said IOC, a plurality of mark bits individual ones of which correspond to one byte of a data buffer used for buffering data during an IOC write to memory operation, individual ones of said mark bits being asserted to indicate that corresponding byte is a byte that is to be written to main memory; and

responsive to a condition wherein none of said plurality of mark bits are asserted, performing a memory read operation.