Method of manufacturing a semiconductor device comprising an insulated gate field effect device

• US 5,378,655 A
• Filed: 03/31/1994
• Issued: 01/03/1995
• Est. Priority Date: 04/01/1993
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Whight, Kenneth R., Hutchings, Keith M.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MASON, DAVID
• Application Number:
  US08/221,293
• Time in Patent Office: 278 Days
• Field of Search: 437/41, 437/67, 437/203, 437/913, 437/44, 257/330-334, 148/DIG. 126
• US Class Current: 438/138
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A mask (4) defining at least one window (4a) is provided on one major surface (1a) of a semiconductor body (1). The semiconductor body (1) is etched to define a groove (5) into a first region (2) of one conductivity type through a second region (3) of the opposite conductivity type. A relatively thin layer of gate insulator (6) is provided on the surface (5a) of the groove (5). A gate conductive region (7) of an oxidizable conductive material is provided within the groove (5) to define with the gate insulator layer an insulated gate structure (8) bounded by a conduction channel-defining area (30) of the second region (3). A step (15) in the surface structure is then defined by causing the insulated gate structure (8) to extend beyond the surrounding surface by oxidizing the exposed (7a) gate conductive material to define an insulating capping region (9) on the gate conductive region (3). A layer (10) is formed over the surface structure and etched anisotropically to leave portions (10a) of the layer on the side wall (8'"'"'a) of the step (15) defined by the insulated gate structure (8) and to define beneath the portions (10a) third regions (11) of the one conductivity type within the second region (3). An electrically conductive layer (12) is deposited to contact both the second and the third regions (3 and 11).

Claims

1. A method of manufacturing a semiconductor device comprising an insulated gate field effect device, which method comprises providing a semiconductor body having first and second major surfaces with a first region of one conductivity type separated from the first major surface by a second region of the opposite conductivity type, providing on the one major surface a mask defining at least one window, etching the semiconductor body through the window to define a groove extending through the second region into the first region, providing a layer of gate insulator on the surface of the groove, providing a gate conductive region of an oxidizable conductive material within the groove to define with the gate insulator layer an insulated gate structure bounded by a conduction channel-defining area of the second region, causing the insulated gate structure to extend beyond the surrounding semiconductor surface to define at least one step in the surface structure by oxidizing the exposed conductive material to define an insulating capping region over the exposed surface of the gate conductive region and then providing a layer over the surface structure, etching the layer anisotropically to leave portions of the layer on the sidewall of the steps defined by the insulated gate structure and to define beneath the portions third regions of the one conductivity type within the second region, and depositing an electrically conductive layer to contact both the second and the third regions.

2. A method according to claim 1, wherein the step of causing the insulated gate structure to extend beyond the surrounding semiconductor surface to define a step in the surface structure further comprises etching back the first major surface using the capping region as a mask to leave areas of the side walls of the insulated gate structure exposed and projecting beyond the etched-back surface.

3. A method according to claim 2, which comprises providing the layer as an insulating layer.

4. A method according to claim 3, which comprises forming a layer of the one conductivity type to separate the second region from the first major surface and continuing the anisotropic etching so as to etch through the layer of the one conductivity type to define the third regions.

5. A method according to claim 4, which comprises forming the layer of the one conductivity type to separate the second region from the first major surface after oxidizing the exposed conductive material.

6. A method according to claim 2, which comprises providing the layer as a layer doped with impurities of the one conductivity type and forming the third region by causing impurities to diffuse out of the portions of the layer left after the anisotropic etching into the second region.

7. A method according to claims 1, which comprises forming the gate conductive region of doped polycrystalline silicon.

8. A method according to claim 7, which comprises providing an anti-oxidation layer on the first major surface before forming the gate conductive region.

9. A method according to claim 8, which comprises forming the gate insulator as an oxide layer covering the first major surface and forming the anti-oxidation layer by introducing nitrogen to convert at least a surface region of the gate oxide layer to a nitrogen oxide layer.

10. A method according to claim 1, which comprises providing an electrically conductive layer on the second major surface so that in operation of the device the main current path is between the first and second major surfaces through the first region.

11. A method according to claim 1, which comprises providing at least one fourth region of the opposite conductivity type spaced from the second region by the first region for injecting charge carriers of the opposite conductivity type into the first region during operation of the device.

12. A method according to claim 1, which comprises defining the window in the mask so that the groove forms a grid-like trench.

13. A method according to claim 2, which comprises forming a layer of the one conductivity type to separate the second region from the first major surface and continuing the anisotropic etching so as to etch through the layer of the one conductivity type to define the third regions.

14. A method according to claim 1, which comprises providing the layer as an insulating layer.

15. A method according to claim 1, which comprises forming a layer of the one conductivity type to separate the second region from the first major surface and continuing the anisotropic etching so as to etch through the layer of the one conductivity type to define the third regions.

16. A method according to claim 15, which comprises forming the layer of the one conductivity type to separate the second region from the first major surface after oxidizing the exposed conductive material.

17. A method according to claim 1, which comprises providing the layer as a layer doped with impurities of the one conductivity type and forming the third region by causing impurities to diffuse out of the portions of the layer left after the anisotropic etching into the second region.