Semiconductor integrated circuit and method and system for designing layout of the same

• US 5,378,904 A
• Filed: 09/17/1991
• Issued: 01/03/1995
• Est. Priority Date: 09/17/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamamoto, Tetsuya, Suzuki, Goro, Okamura, Yoshio, Iwamura, Masahiro
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): Ratliff, Reginald A.
• Application Number:
  US07/760,888
• Time in Patent Office: 1,204 Days
• Field of Search: 357/40, 437/51, 364/491, 364/490, 364/489, 364/488, 257/208, 257/211, 307/465, 307/465.1, 307/482.1
• US Class Current: 257/208
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An LSI layout design method is for placing on a chip a plurality of different master cells, each of which has a plurality of signal wiring conductors not connected to internal elements, for example, transistors, resistors and so on for realizing a certain logic function.

Claims

1. An LSI layout design method comprising the steps of:

providing in advance a plurality of master cells, each master cell including at least one element and a plurality of signal wiring lines which are not connected to any of the elements within the master cell;

arranging said plurality of master cells on a diagram, corresponding to a plan view area of a main surface of a chip;

mutually connecting specified ones of said plurality of signal wiring lines between different ones of the arranged said plurality of master cells in accordance with information of logic circuits to be effected of said LSI; and

connecting, within specified ones of the arranged said plurality of master cells, ones of said plurality of signal wiring lines to respective elements.

12. A layout design method according to claim 1, wherein the step of arranging said plurality of master cells includes arranging said plurality of master cells in accordance with an X-and Y-coordinates system.

13. A layout design method according to claim 12, further comprising the steps of:

assigning to a predetermined signal at least one of said plurality of signal wiring lines of different master cells having the same X-coordinate or Y-coordinate, after said plurality of master cells are arranged; and

connecting the assigned signal wiring line to one or more elements.

19. A layout design method according to claim 12, wherein each one of said plurality of master cells includes the same number of wiring lines.

20. A layout design method according to claim 1, wherein each one of said plurality of master cells includes the same number of wiring lines.

2. An LSI layout design method comprising the steps of:

providing in advance a plurality of master cells, each of which including at least one element and a plurality of signal wiring lines which are not connected to any of the elements within the master cell and each of which having candidates of signal input/output positions;

arranging said plurality of master cells on a diagram, corresponding to a plan view area of a main surface of a chip; and

mutually connecting specified ones of said plurality of signal wiring lines between different ones of the arranged said plurality of master cells in accordance with information of logic circuits to be effected of said LSI.

3. A layout design method according to claim 2, further comprising the step of determining at least one of said candidates of said signal input/output positions of each said master cell, after said plurality of master cells are arranged.

4. An LSI layout design method comprising the steps of:

providing in advance a plurality of master cells, each of which including at least one element and a plurality of signal wiring lines which are not connected to any of the elements within the master cell;

arranging said plurality of master cells on a diagram, corresponding to a plan view area of a main surface of a chip; and

determining two or more from among connection points between neighboring ones of said plurality of master cells, after said plurality of master cells are densely arranged; and

specifying ones of said plurality of signal wiring lines, in each of neighboring master cells, which are to be mutually connected, via the determined connection points, after said plurality of master cells are densely arranged.

5. An LSI layout design method comprising the steps of:

providing in advance a plurality of master cells, each of which including at least one element and a plurality of signal lines which are not connected to any of the elements within the master cell;

densely arranging said plurality of master cells on a diagram, corresponding to a plan view area of a chip, substantially without leaving any gap between adjacently disposed master cells in at least two directions; and

mutually connecting specified ones of said plurality of signal wiring lines between different ones of said plurality of master cells in accordance with information of logic circuits to be effected of said LSI, after said plurality of master cells are densely arranged.

6. A layout design method according to claim 5, wherein said densely arranging step includes the step of removing unnecessary portions in accordance with a design rule to couple the master cells to one another.

14. A layout design method according to claim 6, wherein said at least two directions include vertical and horizontal directions with respect to an X-and Y-coordinates system.

15. A layout design method according to claim 5, wherein said at least two directions include vertical and horizontal directions with respect to an X-and Y-coordinates system.

7. An LSI layout design method comprising the steps of:

providing in advance a plurality of master cells, each master cell including at least one element and a plurality of patterns of signal wiring conductors which are not connected to any of the elements within the master cell;

arranging said plurality of master cells on a diagram, corresponding to a plan view area of a main surface of a chip; and

adding contact patterns or wiring line patterns to a layout pattern of each of the arranged master cells to effect connections between elements and specified ones of said patterns of signal wiring conductors within respective master cells and effect connections between specified ones of said patterns of signal wiring conductors in different ones of the arranged master cells in accordance with information of logic circuits to be effected of said LSI.

8. A layout design method according to claim 7, wherein said adding step includes the step of adding to the arranged master cells wiring line patterns which are long enough to reach a frame of each of the arranged master cells.

9. A layout design method according to claim 7, further comprising the step of removing patterns which are not necessary for realizing a desired logic circuit from each of the arranged master cells.

10. An LSI layout design method comprising the steps of:

providing in advance layout patterns of a plurality of master cells, each master cell including at least one element and patterns of signal wiring conductors which are not connected to any of the elements within the master cell;

assigning each master cell to portions of a logic diagram of a circuit for realizing a desired logic circuit arrangement;

arranging the layout patterns of the assigned master cells on a diagram, corresponding to a plan view area of a main surface of a chip, in accordance with information of positions of the master cells assigned on said logic diagram; and

adding patterns of conductors for effecting connections between specified ones of said patterns of signal wiring conductors in different master cells and between elements and specified ones of said patterns of signal wiring conductors within respective master cells, after said plurality of master cells are arranged.

11. A layout design method for an LSI on a chip, comprising the steps of:

providing in advance a plurality of master cells for different functions, each master cell having a pattern of an element and patterns of signal wiring conductors not connected to the element;

assigning said plurality of master cells to portions of a logic diagram of a circuit for realizing a desired logic circuit arrangement, in accordance with a logical function of each master cell, and to densely arrange the assigned master cells on the logic diagram, corresponding to a plan view area of a main surface of said chip, by vertically and horizontally modifying a position of each assigned master cell; and

adding contact or wiring line patterns to a layout pattern of each of the arranged master cells to effect connections between the pattern of said element and at least one of the patterns of said signal wiring conductors and between patterns of said signal wiring conductors of said arranged master cells.

16. A layout design method according to claim 11, wherein the step of assigning includes arranging the assigned master cells by vertically and horizontally modifying a position, using an X-and Y-coordinates system, of each one thereof to substantially eliminate any gaps between adjacently disposed master cells.

17. A layout design method according to claim 16, wherein each one of said plurality of master cells has the same number of patterns of signal wiring conductors.

18. A layout design method according to claim 11, wherein each one of said plurality of master cells has the same number of patterns of signal wiring conductors.