Semiconductor device with a particular source/drain and gate structure

• US 5,378,914 A
• Filed: 12/24/1992
• Issued: 01/03/1995
• Est. Priority Date: 05/31/1990
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Kochi, Tetsunobu, Ohzu, Hayao
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Fahmy, Wael M.
• Application Number:
  US07/997,135
• Time in Patent Office: 740 Days
• Field of Search: 357/42, 357/23.4, 357/23.3, 357/86, 357/68, 357/23.6, 257/369, 257/618, 257/622, 257/374, 257/370, 257/330, 257/331, 257/332
• US Class Current: 257/369
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

There is provided a semiconductor device with very small functional elements, which can be constructed by necessary minimum components without any unnecessary surface area, thus being capable of significantly reducing the layout area and adapted for achieving a fine geometry and a high level of integration. The semiconductor device is provided with a first semiconductor area of a first conductive type (for example a p^- well) and a second semiconductor area formed on or under the first semiconductor area and having a second conductive type different from the first conductive type (for example a source or drain area), in which an electrode electrically connected to the first semiconductor area is formed through the second semiconductor area, and the first and second semiconductor areas are shortcircuited by the above-mentioned electrode.

Claims

1. A semiconductor device having a semiconductor body provided with a vertical field-effect transistor, which body comprises:

a first semiconductor region and a second semiconductor region of a first conductivity type to provide source and drain regions;

a third semiconductor region of a second conductivity type different from said first conductivity type having an intermediate portion to provide a channel portion and a surface portion;

said first semiconductor region disposed on said intermediate portion;

said third semiconductor region disposed on said second semiconductor region;

a gate electrode separated from said intermediate portion by an insulating material, wherein said source and drain regions and said channel portion are arranged only vertically along a side surface of said gate electrode; and

a buried electrode electrically connected with said second semiconductor region and said third semiconductor region via a through hole penetrating said third semiconductor region, wherein said second region and said third region are thereby short circuited; and

wherein said buried electrode is formed in said body.

2. A semiconductor device according to claim 1, constituting a NOT circuit element.

3. A semiconductor device according to claim 1, constituting a NOR circuit element.

4. A semiconductor device according to claim 1, constituting a NAND circuit element.

5. A semiconductor device according to claim 1, wherein said second semiconductor region is a drain.

6. A semiconductor device according to claim 1, wherein said second semiconductor region is buried within said semiconductor body, and is provided on a substrate of the second conductivity type.

7. A semiconductor device according to claim 6, wherein said buried electrode is contacted with said substrate.

8. A semiconductor device according to claim 1, wherein said second semiconductor region is buried within said semiconductor body, and is provided on a fourth semiconductor region of the second conductivity type.

9. A semiconductor device according to claim 8, wherein said fourth semiconductor region is provided on a substrate of the first conductivity type.

10. A semiconductor device according to claim 1, wherein said buried electrode is made of aluminum.

11. A semiconductor device having a semiconductor body provided with a vertical complementary MOS inverter, said body comprises:

a first semiconductor region and a second semiconductor region of an N conductivity type to provide source and drain regions;

a third semiconductor region of a P conductivity type having an intermediate portion to provide a channel portion and a surface portion;

said first semiconductor region disposed on said intermediate portion;

said third semiconductor region disposed on said second semiconductor region;

a fourth semiconductor region and a fifth semiconductor region of a P conductivity type to provide source and drain regions;

a sixth semiconductor region of an N conductivity type having an intermediate portion to provide a channel portion and a surface portion;

said fourth semiconductor region disposed on said intermediate portion;

said sixth semiconductor region disposed on said fifth semiconductor region;

a common gate electrode separated from said intermediate portions of said third semiconductor region and said sixth semiconductor region by a gate insulator to provide an input-terminal, wherein each of said source and drain regions and said channel portions are arranged only vertically along opposite sides of said common gate electrodes;

a first buried electrode electrically connected with said second semiconductor region and said third semiconductor region which are thereby short circuited; and

a second buried electrode electrically connected with said fifth semiconductor region and said sixth semiconductor region which are thereby short circuited;

wherein said first buried electrode and said second buried electrode are formed in said body.

12. A semiconductor device having a semiconductor body provided with at least two vertical field-effect transistors said body comprising:

at least two first semiconductor regions and a second semiconductor region of a first conductivity type to provide source and drain regions;

a third semiconductor region of a second conductivity type different from said first conductivity type having an intermediate portion to provide at least two channel portions and a surface portion;

said first semiconductor regions disposed on said intermediate portion;

said third semiconductor region disposed on said second semiconductor region;

at least two gate electrodes separated from said intermediate portions by an insulating material, wherein each of said source and drain regions and channel portions are arranged only vertically along a side surface of each said at least two gate electrodes; and

a buried electrode electrically connected with one of said first semiconductor regions and said third semiconductor region via a through hole penetrating the one of said first semiconductor regions, wherein the one of said first region and said third region are thereby short circuited, and wherein said buried electrode is formed in said body.