Digital-to-analog converter

• US 5,379,040 A
• Filed: 02/17/1993
• Issued: 01/03/1995
• Est. Priority Date: 02/17/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kitamura, Yoshiaki, Mizomoto, Hiroyuki
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/018,756
• Time in Patent Office: 685 Days
• Field of Search: 341/136, 341/143, 341/144, 341/150
• US Class Current: 341/143
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation

Abstract

A digital-to-analog converter includes a decoder, a full differential type low-pass filter, and first to fourth switches. The decoder has first and second inputs and first and second outputs. The low-pass filter has first and second inputs and first and second outputs. The first switch has a first terminal connected to a first reference voltage source, a second terminal connected to the first input of the low-pass filter, and a third terminal as a control terminal connected to the first output of the decoder. The second switch has a first terminal connected to the first reference voltage source, a second terminal connected to the second input of the low-pass filter, and a third terminal as a control terminal connected to the second output of the decoder. The third switch has a first terminal connected to a second reference voltage source, a second terminal connected to the second input of the low-pass filter, and a third terminal as a control terminal connected to the first output of the decoder. The fourth switch has a first terminal connected to the second reference voltage source, a second terminal connected to the first input of the low-pass filter, and a third terminal connected to the second output of the decoder.

Claims

1. A digital-to-analog converter comprising:

a decoder having first and second inputs and firsts second and third outputs;

a full differential type low-pass filter having first and second inputs and first and second outputs;

a first switch having a first terminal connected to a first reference voltage source, a second terminal connected to the first input of said full differential type low-pass filter, and a third terminal as a control terminal connected to the first output of said decoder;

a second switch having a first terminal connected to said first reference voltage source, a second terminal connected to the second input of said full differential type low-pass filter, and a third terminal as a control terminal connected to the second output of said decoder;

a third switch having a first terminal connected to a second reference voltage source, a second terminal connected to the second input of said full differential type low-pass filter, and a third terminal as a control terminal connected to the first output of said decoder;

a fourth switch having a first terminal connected to said second reference voltage source, a second terminal connected to the first input of said full differential type low-pass filter, and a third terminal connected to the second output of said decoder;

a fifth switch having a first terminal connected to the first input of said full differential type low-pass filter, a second terminal connected to the second input of said full differential type low-pass filter, and a third terminal as a control terminal connected to the third output of said decoder; and

a sixth switch having a first terminal connected to the second input of said full differential type low-pass filter, a second terminal connected to the first input of said full differential type low-pass filter, and a third terminal as a control terminal connected to the third output of said decoder.

2. A converter according to claim 1, wherein said first, second, and fifth switches are p-channel MOS transistors, and

said third, fourth and sixth switches are n-channel MOS transistors.

3. A digital-to-analog converter comprising:

a decoder having first and second inputs and first and second outputs;

a full differential type low-pass filter having first and second inputs and first and second outputs;

a first inverter circuit for receiving the first output of said decoder as an input;

a second inverter circuit for receiving the second output of said decoder as an input;

a first p-channel MOS transistor having a drain connected to the first input of said full differential type low-pass filter, a source connected to a first reference voltage source, and a gate connected to an output of said first inverter circuit;

a second p-channel MOS transistor having a drain connected to the second input of said full differential type low-pass filter, and a source connected to said first reference voltage source, and a gate connected to an output of said second inverter circuit;

a first n-channel MOS transistor having a drain connected to the second input of said full differential type low-pass filter, a source connected to a second reference voltage source, and a gate connected to the first output of said decoder; and

a second n-channel MOS transistor having a drain connected to the first input of said full differential type low-pass filter, a source connected to said second reference voltage source, and a gate connected to the second output of said decoder.

4. A converter according to claim 3, wherein said decoder has a third output, and

said converter comprises:

a third inverter circuit for receiving the third output of said decoder as an input;

a first switch having a first terminal connected to the first input of said full differential type low-pass filter, a second terminal connected to the second input of said full differential type low-pass filter, and a third terminal connected to the output of said third inverter circuit; and

a second switch having a first terminal connected to the second input of said full differential type low-pass filter, a second terminal connected to the first input of said full differential type low-pass filter, and a third terminal connected to the third output of said decoder.