Digital video signal resolution converting apparatus using an average of blocks of a training signal

• US 5,379,072 A
• Filed: 12/08/1992
• Issued: 01/03/1995
• Est. Priority Date: 12/13/1991
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kondo, Tetsujiro
• Primary Examiner(s): Kostak, Victor R.
• Assistant Examiner(s): Flynn, Nathan J.
• Application Number:
  US07/986,707
• Time in Patent Office: 756 Days
• Field of Search: 358/140, 358/166, 358/11, 358/37, 358/133
• US Class Current: 348/441
• CPC Class Codes: H04N 19/98 Adaptive-dynamic-range coding [ADRC]
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0125 one of the standards being a high definition standard
• CPC Class Codes: H04N 7/0135 involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59

Abstract

A digital video signal converting apparatus for converting a first digital video signal having a first resolution to a second digital video signal having a second resolution higher than the first resolution, comprises; block segmentation circuit for converting the first digital video signal into a block format, memory having a mapping table stored therein and having address terminals to which the first digital video signal in a block format is supplied and output terminals from which the second digital video signal in block format is output, and block separation circuit for converting the second digital video signal in a block format into a digital video signal in a raster scan order, wherein the mapping table in the memory is generated by training utilizing a plurality of images the training step being performed by generating first and second digital video signal corresponding to each of the plurality of images, converting each of the first and second digital video signals into a block format, and selecting the first digital video signal in a block format is an address signal for the mapping table and inputting the second digital video signal in a block format to a memory area corresponding to the address, and generating data of the mapping table from the signal stored in the memory area.

Claims

1. A digital video signal converting apparatus, comprising:

block segmentation means for segmenting a first digital video signal having a first resolution into blocks of video data,

memory means for receiving each of said blocks of video data as respective addresses and for reading out converted data stored in a mapping table at said respective addresses, said mapping table representing a relationship between blocks of a training signal expressed in a second resolution at addresses respectively given by said blocks of said training signal expressed in said first resolution, and

block separation means for deblocking said converted data into a second digital video signal having said second resolution.

2. A digital video signal converting apparatus according to claim 1, wherein said blocks of video data each have first and second spatial dimensions.

3. A digital video signal converting apparatus according to claim 2, wherein said first digital video signal is a signal in accordance with the NTSC standard, and said second digital video signal is a signal having a higher resolution than said first digital video signal.

4. A digital video signal converting apparatus according to claim 2, wherein said blocks of video data each also have a third temporal dimension.

5. A digital video signal converting apparatus according to claim 4, wherein said first digital video signal is a signal in accordance with the PAL standard, and said second digital video signal is a signal in accordance with the NTSC standard.

6. A digital video signal converting apparatus according to claim 1, further comprising block-compression coding means for compressing said blocks of video data, and block decoding means for decompressing said converted data.

7. A digital video signal converting apparatus according to claim 6, wherein said block compression coding means is an ADRC encoder.

8. A digital video signal converting apparatus according to claim 1, wherein said mapping table includes interpolated data in place of zero value data.

9. A digital video signal converting apparatus according to claim 1, wherein said second resolution is higher than said first resolution.

10. A digital video signal converting apparatus according to claim 1, wherein said mapping table represents an average of said blocks of said training signal expressed in said second resolution at said addresses respectively given by said blocks of said training signal in said first resolution.