Compact adapter package providing peripheral to area translation for an integrated circuit chip

• US 5,379,191 A
• Filed: 06/09/1994
• Issued: 01/03/1995
• Est. Priority Date: 02/26/1991
• Status: Expired due to Term

• Current Assignee: Stovokor Technology LLC (Intellectual Ventures LLC)
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Whalen, Barry H., Carey, David H.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/257,235
• Time in Patent Office: 208 Days
• Field of Search: 228/180.21, 228/180.22, 257/700, 257/723, 257/777, 257/778, 257/774, 257/728, 361/760, 361/764, 361/767, 361/768, 361/770, 361/771, 361/777, 361/807, 361/808, 361/809, 437/209, 439/44, 439/65, 439/66, 439/68, 439/69, 439/74, 439/83
• US Class Current: 361/777
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Claims

1. A compact adapter package providing peripheral to area translation for an integrated circuit chip, comprising:

a single integrated circuit chip having top and bottom surfaces and having a plurality of conductive terminals disposed on the bottom surface wherein the entire bottom surface of the chip forms a major surface area of the chip and a portion of the major surface area inside the terminals towards the center of the chip forms an inner surface area of the chip;

a dielectric support having upper and lower surfaces wherein the support is positioned entirely within the inner surface area of the chip and the bottom surface of the chip is spaced from and faces the upper surface of the support;

a plurality of electrically conductive pads extending laterally from the upper surface of the support wherein the pads are aligned with and bonded in one-to-one relationship to the terminals thereby attaching the chip to the support wherein the pads, terminals and bonds are positioned entirely within the major surface area of the chip outside the inner surface area of the chip;

a plurality of flat electrically conductive horizontal reroute lines on the upper surface of the support wherein each reroute line includes a first end at one of said pads and a second end within the inner surface area of the chip wherein the reroute lines are positioned entirely within the major surface area of the chip and disposed entirely above and parallel to the upper surface of the support;

a plurality of electrically conductive vertical vias extending through the support between the upper and lower surfaces of the support wherein each via is positioned entirely within the inner surface area of the chip and positioned directly beneath and electrically connected to the second end of one of said reroute lines; and

a plurality of coupling elements in an array pattern on the bottom surface of the support wherein each coupling element is positioned entirely within the inner surface area of the chip and includes a portion directly beneath and electrically connected to one of said vias such that each terminal is electrically connected to one of said coupling elements;

wherein each terminal is electrically connected to a single pad, reroute line, via and coupling element, the reroute lines provide all horizontal translation between the terminals and the coupling elements, and the vias provide all vertical translation between the terminals and the coupling elements.

2. The adapter package of claim 1 wherein the bonds between the terminals and the pads constitute the sole means for attaching the chip to the support.

3. The adapter package of claim 1 wherein the support is a flexible tape-automated-bonding frame.

4. A compact adapter package providing peripheral to area translation for an integrated circuit chip, comprising:

a single integrated circuit chip having top and bottom surfaces and having a plurality of conductive terminals disposed on the bottom surface wherein the entire bottom surface of the chip forms a major surface area of the chip and a portion of the major surface area inside the terminals towards the center of the chip forms an inner surface area of the chip;

a dielectric support having upper and lower surfaces wherein the support is positioned entirely within the inner surface area of the chip and the bottom surface of the chip is spaced from and faces the upper surface of the support;

a compressible supportive insulator between the bottom surface of the chip and the upper surface of the support wherein the compressible supportive insulator is positioned entirely within the inner surface area of the chip and outer sidewalls of the compressible supportive insulator are aligned with outer sidewalls of the support;

a plurality of electrically conductive pads extending laterally from the upper surface of the support wherein the pads are aligned with and bonded in one-to-one relationship to the terminals thereby attaching the chip to the support wherein the pads, terminals and bonds are positioned entirely within the major surface area of the chip outside the inner surface area of the chip;

a plurality of flat electrically conductive horizontal reroute lines on the upper surface of the support wherein each reroute line includes a first end at one of said pads and a second end within the inner surface area of the chip wherein the reroute lines are positioned entirely within the major surface area of the chip and disposed entirely above and parallel to the upper surface of the support;

a plurality of electrically conductive vertical vias extending through the support between the upper and lower surfaces of the support wherein each via is positioned entirely within the inner surface area of the chip and positioned directly beneath and electrically connected to the second end of one of said reroute lines; and

a plurality of coupling elements in an array pattern on the bottom surface the support wherein each coupling element is positioned entirely within the inner surface area of the chip and includes a portion directly beneath and electrically connected to one of said vias such that each terminal is electrically connected to one of said coupling elements;

wherein each terminal is electrically connected to a single pad, reroute line, via and coupling element, the reroute lines provide all horizontal translation between the terminals and the coupling elements, and the vias provide all vertical translation between the terminals and the coupling elements.

5. The adapter package of claim 4 wherein the compressible supportive insulator contacts the bottom surface of the chip, the upper surface of the support and the reroute lines.

6. The adapter package of claim 4 wherein the compressible supportive insulator is selected from the group consisting of silicone, rubber and elastomeric polymer foam.

7. The adapter package of claim 4 wherein the bonds between the terminals and the pads constitute the sole means for attaching the chip to the support.

8. The adapter package of claim 4 wherein the support is a flexible tape-automated-bonding frame.