Semiconductor integrated circuit device having a memory and an operational unit integrated therein

• US 5,379,257 A
• Filed: 09/30/1991
• Issued: 01/03/1995
• Est. Priority Date: 11/16/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Segawa, Hiroshi, Ishihara, Kazuya, Yoshimoto, Masahiko, Matsumura, Tetsuya, Uramoto, Shinichi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/767,767
• Time in Patent Office: 1,191 Days
• Field of Search: 365/189.01, 365/189.05, 365/189.09, 365/189.07, 364/DIG. 1, 395/425, 395/132, 395/166
• US Class Current: 365/189.011
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.

Claims

1. A semiconductor integrated circuit device comprising:

a memory cell array including a plurality of memory cell groups, each of said memory cell groups including a plurality of bit arrays each having memory cells arranged in a matrix form of at least one column and a plurality of rows, the memory cells of each of said plurality of bit arrays of said plurality of memory cell groups being arranged adjacent to the memory cells of a bit array of another memory cell group;

a plurality of selecting means provided corresponding to said plurality of memory cell groups in said memory cell array, respectively, and responsive to address signals applied independently for said groups for selecting memory cells designated by said address signals from corresponding memory cell groups; and

operational means, responsive to a stored information read out from the memory cells in at least one memory cell group for performing a predetermined operation.

2. A semiconductor integrated circuit device according to claim 1, wherein said operational means includes a plurality of operational circuits provided corresponding to respective bit arrays of said memory cell groups.

3. A semiconductor integrated circuit device according to claim 2, wherein each of said plurality of memory cell groups stores a different group of data words, each data word including a plurality of data bits,

each bit array in a corresponding memory cell group stores data bits of an identical digit of the data words, and

bit arrays storing the data bits of the identical digit are arranged adjacent one another to provide one subarray in said memory cell array.

4. A semiconductor integrated circuit device according to claim 1, wherein said bit arrays store corresponding data bits of one data word in identical storage positions.

5. A semiconductor integrated circuit device according to claim 3, further comprising data input means provided corresponding to said plurality of groups, respectively, for receiving input data for corresponding groups, said data input means including input circuits provided corresponding to said bit arrays, respectively.

6. A semiconductor integrated circuit device according to claim 5, wherein said selecting means include selectors each disposed between one of said input circuits and a corresponding bit array, each of said selectors being responsive to a related applied address signal to connect a column in a corresponding bit array to a corresponding input circuit.

7. A semiconductor integrated circuit device according to claim 3, further comprising data output circuits one corresponding to each of said bit arrays for transmitting the data of selected memory cells in a corresponding bit array to a corresponding input circuit.

8. A semiconductor integrated circuit device according to claim 7, wherein said selecting means include selectors one corresponding to each of said bit arrays, each of said selectors being responsive to a related address signal to connect one column in a corresponding bit array to a corresponding output circuit.

9. A semiconductor integrated circuit device according to claim 2, further comprising buffer circuits one corresponding to each of said operational circuits, and responsive to an output control signal to transmit output of a corresponding operational circuit, each said buffer circuit changing its output to an output high impedance state when disabled.

10. A semiconductor integrated circuit device according to claim 2, further comprising buffer circuits one corresponding to each of said bit arrays, and responsive to an output control signal to output the data of selected memory cells in a corresponding bit array with a corresponding operational circuit bypassed.

11. A semiconductor integrated circuit device according to claim 3, wherein said plurality of operational circuits include adders provided corresponding to said subarrays for adding the data of selected memory cells in the bit arrays included in corresponding subarrays.

12. A semiconductor integrated circuit device according to claim 11, further comprising multiplexer circuits each disposed between each respective said operational circuits and each respective said subarrays, each of said multiplexer circuits being responsive to a select signal for selectively allowing passage of two data selected from (i) an output of a corresponding operational circuit and (ii) data from the output of a respective bit array in a corresponding subarray, to a corresponding operational circuit.

13. A semiconductor integrated circuit memory device on a single chip, comprising:

a single array of memory cells arranged in a matrix of rows and columns, said memory cell array divided into first and second groups of memory cell columns, each group of memory cell columns comprising a plurality of bit arrays each formed of a predetermined number of columns of memory cells in adjacent positions, the predetermined number of columns of memory cells in adjacent positions comprising each of the bit arrays of said first group being interdigitated alternately with the predetermined number of columns of memory cells in adjacent positions comprising each of the bit arrays of said second group,

first and second means corresponding respectively to said first and second groups and each responsive to an address signal for selecting one of said rows of memory cells for each group and for selecting one memory cell in each bit array in a selected row in each said group for access, each such selected cell located in the same column position in the respective bit array;

reading means for reading data stored in selected cells; and

operational means comprising a plurality of operational circuits, each corresponding to a respective bit array, for performing a predetermined operation on data provided by said reading means.

14. A semiconductor integrated circuit memory device as recited in claim 13, wherein said operational circuits comprise adding circuits for adding data provided by said reading means from said first Group with data provided by said reading means from said second group.

15. A semiconductor integrated circuit memory device as recited in claim 13, further comprising multiplexer means for receiving data from both said groups provided by said reading means, said multiplexer means having an output connected to said operational means.

16. A semiconductor integrated circuit device comprising:

a memory cell array including a plurality of memory cell groups, each of said memory cell groups including a plurality of bit arrays each having memory cells arranged in a matrix form of at least one column and a plurality of rows, the memory cells of each of said plurality of bit arrays of said plurality of memory cell groups being arranged adjacent to the memory cells of a bit array of another memory cell group;

a plurality of selecting means provided corresponding to said plurality of memory cell groups in said memory cell array, respectively, and responsive to address signals applied independently for said groups for selecting memory cells designated by said address signals from corresponding memory cell groups; and

a plurality of operation circuits each provided corresponding to respective bit arrays of the memory cell groups.

17. A semiconductor integrated circuit device according to claim 16, wherein each of said plurality of memory cell groups stores a different group of data words, each data word including a plurality of data bits,

each bit array in a corresponding memory cell group stores data bits of an identical digit of the data words, and

bit arrays storing the data bits of the identical digit are arranged adjacent one another to provide one subarray in said memory cell array.

18. A semiconductor integrated circuit device according to claim 17, further comprising data input means provided corresponding to said plurality of groups, respectively, for receiving input data for corresponding groups, said data input means including input circuits provided corresponding to said bit arrays, respectively.

19. A semiconductor integrated circuit device according to claim 18, wherein said selecting means include selectors each disposed between one of said input circuits and a corresponding bit array, each of said selectors being responsive to a related applied address signal to connect a column in a corresponding bit array to a corresponding input circuit.

20. A semiconductor integrated circuit device according to claim 17, further comprising data output circuits one corresponding to each of said bit arrays for transmitting the data of selected memory cells in a corresponding bit array to a corresponding bit array to a corresponding input circuit.

21. A semiconductor integrated circuit according to claim 20, wherein said selecting means include selectors one corresponding to each of said bit arrays, each of said selectors being responsive to a related address signal to connect one column in a corresponding bit array to a corresponding output circuit.

22. A semiconductor integrated circuit device according to claim 17, wherein said plurality of operational circuits include adders provided corresponding to said subarrays for adding the data of selected memory cells in the bit arrays included in corresponding subarrays.

23. A semiconductor integrated circuit device according to claim 22, further comprising multiplexer circuits each disposed between each respective said operational circuits and each respective said subarrays, each of said multiplexer circuits being responsive to a select signal for selectively allowing passage of two data selected from (i) an output of a corresponding operational circuit and (ii) data from the output of a respective bit array in a corresponding subarray, to a corresponding operational circuit.

24. A semiconductor integrated circuit device according to claim 16, wherein said bit arrays store corresponding data bits of one data word in identical storage positions.

25. A semiconductor integrated circuit device according to claim 16, further comprising buffer circuits one corresponding to each of said operational circuits, and responsive to an output control signal to transmit output of a corresponding operational circuit, each said buffer circuit changing its output to an output high impedance state when disabled.

26. A semiconductor integrated circuit device according to claim 16, further comprising buffer circuits one corresponding to each of said bit arrays, and responsive to an output control signal to output the data of selected memory cells in a corresponding bit array with a corresponding operational circuit bypassed.

38. A semiconductor integrated circuit device according to claim 16, further comprising buffer circuits one corresponding to each of said bit arrays, and responsive to an output control signal to output the data of selected memory cells in a corresponding bit array with a corresponding operational circuit bypassed.

27. A semiconductor integrated circuit device comprising:

a memory cell array including a plurality of memory cell groups, each of said memory cell groups including a plurality of bit arrays with each bit array having memory cells arranged in a matrix form of a plurality of rows and a plurality of columns, the memory cells of each of said plurality of bit arrays of said plurality of memory cell groups being arranged adjacent to the memory cells of a bit array of another memory cell group;

a plurality of selecting means each provided corresponding to each bit array of each memory cell group in said memory cell array for selecting one column in each bit array, and responsive to address signals applied independently for said groups for selecting memory cells designated by said address signals from corresponding memory cell groups; and

a plurality of operation circuits each provided corresponding to the bit arrays of each group having the same column position.

28. The semiconductor integrated circuit device according to claim 27, further including a plurality of amplifier means each provided corresponding to each bit array of each memory cell group in said memory cell array and connected between a respective selecting means and operational circuit.

29. A semiconductor integrated circuit device according to claim 27, wherein each of said plurality of memory cell groups stores a different group of data words, each data word including a plurality of data bits,

each bit array in a corresponding memory cell group stores data bits of an identical digit of the data words, and

bit arrays storing the data bits of the identical digit are arranged adjacent one another to provide one subarray in said memory cell array.

30. A semiconductor integrated circuit according to claim 29, further comprising data input means provided corresponding to said plurality of groups, respectively, for receiving input data for corresponding groups, said data input means including input circuits provided corresponding to said bit arrays, respectively.

31. A semiconductor integrated circuit device according to claim 30, wherein said selecting means include selectors each disposed between one of said input circuits and a corresponding bit array, each of said selectors being responsive to a related applied address signal to connect a column in a corresponding bit array to a corresponding input circuit.

32. A semiconductor integrated circuit device according to claim 27, further comprising data output circuits one corresponding to each of said bit arrays for transmitting the data of selected memory cells in a corresponding bit array to a corresponding bit array to a corresponding input circuit.

33. A semiconductor integrated circuit according to claim 27, wherein said selecting means include selectors one corresponding to each of said bit arrays, each of said selectors being responsive to a related address signal to connect one column in a corresponding bit array to a corresponding output circuit.

34. A semiconductor integrated circuit device according to claim 27, wherein said plurality of operational circuits include adders provided corresponding to said subarrays for adding the data of selected memory cells in the bit arrays included in corresponding subarrays.

35. A semiconductor integrated circuit device according to claim 27, further comprising multiplexer circuits each disposed between each respective said operational circuits and each respective said subarrays, each of said multiplexer circuits being responsive to a select signal for selectively allowing passage of two data selected from (i) an output of a corresponding operational circuit and (ii) data from the output of a respective bit array in a corresponding subarray, to a corresponding operational circuit.

36. A semiconductor integrated circuit device according to claim 27, wherein said bit arrays store corresponding data bits of one data word in identical storage positions.

37. A semiconductor integrated circuit device according to claim 27, further comprising buffer circuits one corresponding to each of said operational circuits, and responsive to an output control signal to transmit output of a corresponding operational circuit, each said buffer circuit changing its output to an output high impedance state when disabled.