Video compression/decompression processing and processors
First Claim
1. A vision processor, comprising:
- an image memory having two read ports and a write port;
a block prediction error memory having two read ports and a write port;
a discrete cosine transform ("DCT") memory configurable as a two read, two write port memory and as a four read, four write port memory;
a shifter having an input coupled to a read port of said search memory, and an output;
a shifter/transposer having an input selectively coupled to one of the other read port of said search memory and to two read ports of said DCT memory configured as a two read, two write port memory;
an arithmetic logic unit having;
a first input selectively coupled to one of the two read ports of said frame memory, to the output of said shifter, and to two read ports of said DCT memory configured as a four read, four write port memory, anda second input selectively coupled to one of the outputs of said shifter and said shifter/transposer, to the output of said shifter/transposer, and to the other two read ports of said DCT memory configured as a four read, four write port memory; and
an output selectively configurable as an average of operandi and a difference of operandi coupled to the write ports of said image memory and block/prediction error memory;
an output configured as an absolute difference of operandi; and
an output configured as a sum of operandi and a difference of operandi coupled to the write ports of said DCT memory;
a tree adder having an input coupled to the absolute difference output of said arithmetic logic unit; and
a multiplier-accumulator having an input coupled to the four read ports of said DCT memory configured as a four read, four write port memory.
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Accused Products
Abstract
A vision processor includes a control section, a motion estimation section, and a discrete cosine transform ("DCT") section. The motion estimation section includes two memories, an image memory with two read ports and a write port, and a search memory with two read ports and a write port. The DCT section includes a DCT memory configurable as a two read, two write port memory and as a four read, four write port memory. The ports of these memories are selectively applied to various elements in the motion estimation path and the DCT path. In motion vector searching, the ALU performs averaging and difference operations on pixels in the frame and search memories. Data from the search memory is shifted for certain operations, before arithmetic operations in the ALU are performed. In DCT operations, transposition is done on word data read from the DCT memory in a shifter/transposer, which is shared with the motion estimation section, and the results written back to the DCT memory through the ALU operating in pass through mode. Multiply-accumulate operations are done in a multiplier-accumulator, which reads and writes-back to the DCT memory. Data transfers from the frame and search memories to the DCT memory may be performed in parallel with multiply-accumulate operations.
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Citations
9 Claims
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1. A vision processor, comprising:
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an image memory having two read ports and a write port; a block prediction error memory having two read ports and a write port; a discrete cosine transform ("DCT") memory configurable as a two read, two write port memory and as a four read, four write port memory; a shifter having an input coupled to a read port of said search memory, and an output; a shifter/transposer having an input selectively coupled to one of the other read port of said search memory and to two read ports of said DCT memory configured as a two read, two write port memory; an arithmetic logic unit having; a first input selectively coupled to one of the two read ports of said frame memory, to the output of said shifter, and to two read ports of said DCT memory configured as a four read, four write port memory, and a second input selectively coupled to one of the outputs of said shifter and said shifter/transposer, to the output of said shifter/transposer, and to the other two read ports of said DCT memory configured as a four read, four write port memory; and an output selectively configurable as an average of operandi and a difference of operandi coupled to the write ports of said image memory and block/prediction error memory; an output configured as an absolute difference of operandi; and an output configured as a sum of operandi and a difference of operandi coupled to the write ports of said DCT memory; a tree adder having an input coupled to the absolute difference output of said arithmetic logic unit; and a multiplier-accumulator having an input coupled to the four read ports of said DCT memory configured as a four read, four write port memory. - View Dependent Claims (2, 3)
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4. A vision processor comprising:
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a first memory for storing image blocks during motion estimation operations, intermediate blocks during interpolation operations, and image blocks and prediction error data during DCT computation operations; a second memory for storing a search window; a third memory for storing pixel data and DCT coefficient data during intraframe conversion operations, a quantizer matrix during multiple quantization operations, and pixel data during general filter computation operations; a DCT transform unit coupled to an output of the third memory for receiving pixel data, and coupled to an input of the third memory for writing DCT coefficients for the received pixel data thereto; a quantization unit coupled to an output of the third memory for receiving DCT coefficients and a quantizer matrix, and coupled to an input of the third memory for writing quantized levels for the received DCT coefficients thereto; a motion estimation unit coupled to outputs of the first and second memories for receiving a image block and a search window, respectively, and coupled to an input of the second memory for writing a best match block thereto; a prediction error unit coupled to outputs of the first and second memories for receiving an image block and a best match block, respectively, and coupled to an input of the first memory for writing prediction error data thereto; and an interpolation unit coupled to an output of the first memory for receiving intermediate blocks during the interpolation operations, and coupled to an input of the first memory for writing interpolated blocks thereto. - View Dependent Claims (5, 6, 7, 8, 9)
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Specification