Uni and bi-directional signal transfer modes in peripheral controller and method of operating same

• US 5,379,382 A
• Filed: 04/21/1992
• Issued: 01/03/1995
• Est. Priority Date: 04/22/1991
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Pilkington Micro-Electronics Limited
• Inventors: Jones, Gareth J., Work, Gordon S., Albiez, Peter A.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US07/871,518
• Time in Patent Office: 987 Days
• Field of Search: 395/200, 395/275, 395/325, 395/500
• US Class Current: 710/63
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A peripheral controller is described which is suitable for connecting a selected one of a plurality of peripheral devices to a computer system. The peripheral controller comprises programmable bidirectional line driver/receiver devices which can be operated in an input only mode, an output only mode or a bidirectional mode and which can be set into an appropriate mode by configuration control data sent from the computer system to the peripheral controller. The peripheral controller also includes a re-configurable logic array which can be configured under the control of the configuration control data to implement a particular interface required for the selected peripheral device. This increases the efficiency of use of a peripheral interface.

Claims

1. A peripheral controller suitable for connecting a selected one of a plurality of peripheral devices to a computer system comprising a processor, a memory and a direct memory access controller interconnected by a system control bus, the peripheral controller comprising a plurality of programmable line driver/receiver devices each capable of operating selectively in a unidirectional signal transfer mode in which the transfer of signals between the computer system and the selected peripheral device is in a selected one of input and output directions and in a bidirectional signal transfer mode when the transfer of said data is in both said input and output directions;

and a re-configurable logic array adapted to be configured to implement a particular interface required for the selected peripheral device under the control of configuration control data generated by the processor and communicated to the peripheral controller, said configuration control data also being useable to place at least one of the programmable line driver/receiver devices into an appropriate one of said signal transfer modes whereby the peripheral controller is capable of implementing transfer of signals between the computer system and the selected peripheral device under the control of the processor.

2. A peripheral controller as claimed in claim 1, which further comprises programmable clock generation means including frequency synthesis means.

3. A peripheral controller as claimed in claim 1 which further comprises a synchronisation generator capable of producing a synchronisation signal to enable the computer system to communicate with the peripheral controller in an asynchronous manner, said synchronisation generator being operable to resolve metastable conditions.

4. A peripheral controller as claimed in claim 1 further comprising programmable communication registers arranged to be used in the transfer of data and control words between the computer system and the particular interface implemented on the configurable logic array.

5. A peripheral controller as claimed in claim 1 further comprising a communication flag port connected between the configurable logic array and the direct memory access controller via the system control bus and adapted to control communication between the configurable logic array and the host computer system.

6. A peripheral controller as claimed in claim 1 further comprising an internal data bus and a configuration control bus arranged to receive data from the system control bus under the control of a bus interface for the distribution of the configuration control data to the configurable logic array and the programmable line driver/receiver devices and to the programmable communication registers, the synchronisation generator, the clock generator and the communication flag port, when present, to configure the peripheral controller.

7. A peripheral controller as claimed in claim 6 in which the communication flag port in operation may be enabled/disabled under control of the bus interface.

8. A peripheral controller as claimed in claim 1 in which the configurable logic array is of a type claimed in U.K. Pat. No. 2180382B.

9. A peripheral controller as claimed in claim 2 in which the frequency synthesis means comprises:

a voltage controlled oscillator producing an output signal and a compare signal at a frequency dependent on a control voltage;

input clock divider means for producing a first clock signal;

a phase comparator for comparing the phase of the first clock signal with a second clock signal and producing the control voltage in dependence on the phase difference;

a counter and comparator means for providing said second clock signal when a count of pulses of the compare signal equals a preset number.

10. A peripheral controller as claimed in claim 1 in which each programmable line driver/receiver device comprises:

means for selecting the direction of a line signal when operating in said bidirectional signal transfer mode.

11. A peripheral controller as claimed in claim 10 in which each programmable line driver/receiver device comprises input/output multiplexing means.

12. A peripheral controller as claimed in claim 10 in which each programmable line driver/receiver device comprises a programmable output current drive selector having independently programmable current sink and source arrangements.

13. A peripheral controller as claimed in claim 10 in which each programmable line driver/receiver device comprises a programmable input voltage threshold level selector.

14. A peripheral controller as claimed in claim 10 in which each programmable line driver/receiver device comprises programmable value pull up and down resistors for signal termination.

15. A peripheral controller as claimed in claim 10 in which each programmable line driver/receiver device comprises storage means for retaining programmable line driver/receiver configuration data.

16. A peripheral controller as claimed in claim 1 and fabricated as a single semiconductor integrated circuit device.

17. A microcomputer system incorporating a peripheral controller according to claim 1.

18. A method of operating a computer system comprising a processor, a memory, a direct memory access controller, a peripheral controller and a plurality of peripheral devices connected to the peripheral controller, the peripheral controller comprising a plurality of programmable line driver/receiver devices each capable of operating selectively in a unidirectional signal transfer mode in which the transfer of signals to and from the selected peripheral device is in a selected one of input and output directions and in a bidirectional signal transfer mode when the transfer of said signals is in both said input and output directions, the processor, memory, direct memory access controller and peripheral controller being interconnected by a processor system control bus, the computer system further comprising a reconfigurable logic array adapted to be configured to implement a particular interface required for the selected peripheral device, wherein the method comprises the steps of:

communicating a configuration file from the processor over the processor system control bus;

programming said programmable line driver/receiver devices to place at least one of the programmable line driver/receiver devices into an appropriate one of said signal transfer modes; and

configuring said reconfigurable logic array thereby to configure the peripheral controller in accordance with the interface requirements of a selected one of the peripheral devices.