Arithmetic unit for structure arithmetic
First Claim
1. A method for structural arithmetic processing, including:
- a) storing data words in several registers,each data word having a mark part and an information part,said mark part including a mark indicating if the register in question being in use or not,b) said data words being arranged in lists,storing each of said lists in a predetermined number of said registers,said mark part of each of said words in said lists stored in said registers being marked in use indicating that one of said lists has at least a part stored in a register, said list having a part stored in said register including a list instruction denoting which kind of list it is,c) arranging said lists stored in said registers as a tree of lists, of which one of the lists is a root list, where a relation between said lists is determined from an arrangement of said lists in said registers,d) controlling said registers and making use of said list instructions belonging to lists stored in said registers to rearrange said lists among said registers and to perform input/output operations of register content in accordance with said list instructions, wherein an information regarding what kind of structural arithmetic processing to perform can be derived from a type of said root list.
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Accused Products
Abstract
A method and an arithmetic unit for structural arithmetic processing is described. Data words are stored in several registers, each data word having a mark part and an information part. The mark part includes a mark indicating if the register in question being in use or not. The data words are arranged in lists. Each of the lists is stored in a predetermined number of the registers. The mark part of each of the words in the lists stored in the registers is marked in use indicating that one of the lists has at least a part stored in the actual register. The list having a part stored in said actual register includes a list instruction denoting which kind of list it is and the relation between the lists is apparent from the arrangement of the lists in the registers. The registers are controlled by a control device making use of the list instructions belonging to lists stored in the registers to rearrange the lists among the registers and for input/output of register content in accordance with the list instructions.
49 Citations
53 Claims
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1. A method for structural arithmetic processing, including:
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a) storing data words in several registers, each data word having a mark part and an information part, said mark part including a mark indicating if the register in question being in use or not, b) said data words being arranged in lists, storing each of said lists in a predetermined number of said registers, said mark part of each of said words in said lists stored in said registers being marked in use indicating that one of said lists has at least a part stored in a register, said list having a part stored in said register including a list instruction denoting which kind of list it is, c) arranging said lists stored in said registers as a tree of lists, of which one of the lists is a root list, where a relation between said lists is determined from an arrangement of said lists in said registers, d) controlling said registers and making use of said list instructions belonging to lists stored in said registers to rearrange said lists among said registers and to perform input/output operations of register content in accordance with said list instructions, wherein an information regarding what kind of structural arithmetic processing to perform can be derived from a type of said root list. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 39, 40, 41, 45, 46, 47, 48)
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17. A method according to claim 15, wherein a transpose instruction is executed such that an instruction transpose having a three level structure ##EQU9## where the instruction transpose is written into the auxiliary register and the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix, in the matrix of base registers, such that the base register complex contains a square of elements, is rewritten by control from a control unit into the two level structure ##EQU10## where the auxiliary register values are made empty and the information elements in the matrix of base registers are transposed to be placed in a mirror position in relation to a diagonal through the matrix.
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18. A method according to claim 15, wherein a swap instruction is executed such that an instruction swap having a three level structure ##EQU11## where the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix of base registers, such that the base register complex contain a square of elements, is rewritten by control from a control unit into a two level structure ##EQU12## such that the element (em,1, . . . ) changes place with the element (em+1,1, . . . ).
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19. A method according to claim 15, wherein a skip instruction is executed such that an instruction skip having a three level structure ##EQU13## where the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix of base registers is rewritten by control from a control unit into ##EQU14## such that the element (em,1, . . . ) is deleted.
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39. An arithmetic unit according to claim 6, wherein each register cell in a register comprises:
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a) an internal one-bit register (rR), b) at least one internal one-wire bus (aR, bR) connectable to said one-bit register, c) at least one internal, controllable connection, each including a switch (SWN, SWE, SWVi, SWVo, SWHi, SWHo, SWDb, SWa0, SWa1, SWb0, SWb1) controllable by said control means (6p) making one of said at least one one-wire bus connectable to one of following elements;
a bus outside the cell, one of the cells belonging to another of said registers.
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40. An arithmetic unit according to claim 39, wherein said at least one internal one-bit register (rR) includes an input buffer means (Q1), such as an inverter, and an output buffer means (Q2), such as an inverter, and a controllable switch (SWQ) connected between said buffer means.
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41. An arithmetic unit according to claim 40, wherein said input buffer means and said output buffer means are separately connectable to said at least one internal one-wire bus (aR, bR) by controllable switches.
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45. An arithmetic unit according to claim 40, wherein each inverter includes one of the following arrangements:
- two complementary MOS-FETs (FIG. 9C), two MOS-FET of enhancement type (FIG. 9A), one MOS-FET of enhancement type and one MOS-FET of depletion type (FIG. 9B).
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46. An arithmetic unit according to claim 40, wherein a comparator (G1, G2) is connected to compare the content in said part registers and provide the compared result to a wire in an external bus called access.
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47. An arithmetic unit according to claim 46, wherein said comparator comprises:
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a) a first NAND gate having a first input connected to the side of said first buffer means (Q1) turned from said internal register switch and a second input connected to the junction between said internal register switch and said second buffer means (Q2), b) a second NAND gate having a first input connected to the side of said second buffer means (Q2) turned from said internal register switch and a second input connected to the junction between said internal register switch and said first buffer means (Q1); the outputs of said NAND gates being interconnected and connected to said external bus wires in said bus called access.
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48. An arithmetic unit according to claim 47, wherein each of said NAND gates includes two series coupled MOS-FET transistors having series coupled source/drain paths, their gates being the NAND gate inputs, and the drain of the topmost MOS-FET transistor being the output to said external bus wire.
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20. An arithmetic unit for structural arithmetic processing, comprising:
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a) at least one input/output means (v0, v1, v2, v3, id, env) for input and output of data lists, b) several registers (S0,0 to S3,3, F0 to F3, ID, ENV) each being adapted to store a data word, said data words being arranged in said lists, each data word having a mark part and an information part, said mark part including a mark specifying if a register containing said data word is in use or not, each said data lists being storable in a predetermined number of said registers, said mark part of each said register among said registers being marked in use indicating that one of said lists has at least a part stored in said register, said list having a part stored in said register includes a list instruction denoting which kind of list it is, said list parts stored in said registers being arranged as a tree of list parts, of which one of the list parts is a root list part, a relation between said list parts being apparent from an arrangement of said list parts in said registers, c) control means (6p) for controlling said registers and for making use of said list instructions belonging to list parts stored in said registers to rearrange said lists among said registers and for performing input/output operations of register content in accordance with said list instructions, forming an array of said registers (S0,0 to S3,3) having a predefined register (S0,0 to S3,0) for storing said root list part and a predefined set of registers for storing sublist parts, said array being automatically controlled by said control means (6p) to make a structure reduction of data objects placed in said registers in a rewrite operation performed in one register transfer cycle. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 42, 43, 44, 49, 50, 51, 52, 53)
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50. An arithmetic unit according to claim 27, wherein a transpose instruction is adapted to be executed such that an instruction transpose having a three level structure ##EQU15## where the instruction transpose is written into the auxiliary register and the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix, in the matrix of base registers, such that the base register complex contains a square of elements, is adapted to be rewritten by control from said control means into ##EQU16## where the auxiliary register values are made empty and the information elements in the matrix of base registers are transposed to be placed in a mirror position in relation to a diagonal through the matrix.
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51. An arithmetic unit according to claim 27, wherein a swap instruction is adapted to be executed such that an instruction swap having a three level structure ##EQU17## where the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix of base registers, such that the base register complex contain a square of elements, is adapted to be rewritten by control from said control means into ##EQU18## such that the element (em,1, . . . ) changes place with the element (em+1,1, . . . ).
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52. An arithmetic unit according to claim 27, wherein a skip instruction is adapted to be executed such that an instruction skip having a three level structure ##EQU19## where the list of lists of instruction elements ei,j, i and j being the denotations of the positions of the instruction elements in said matrix of base registers, such that the base register complex contain a square of elements, is adapted to be rewritten by control from said control means into ##EQU20## such that the element (em,1, . . . ) is deleted.
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53. An arithmetic unit according to claim 20, wherein it is a part of a central processing unit.
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Specification