FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit

• US 5,379,399 A
• Filed: 05/08/1992
• Issued: 01/03/1995
• Est. Priority Date: 10/17/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Smith, Peter M., Conway-Jones, David C.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Asta, Frank J.
• Application Number:
  US07/880,440
• Time in Patent Office: 970 Days
• Field of Search: 395/425, 364/200 MS File, 364/900 MS File, 345/197, 345/204, 377/41, 307/464, 365/221, 365/189.07
• US Class Current: 711/109
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2205/108 Reading or writing the data blockwise, e.g. using an extra end-of-block pointer
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written. Because different thresholds are assoicated with the portions, data, such as a digitized video signal having active line portions separated by control portions for example, can be transferred via the FIFO from one system to another more efficiently in terms of communication bandwidth usage.

Claims

1. A FIFO memory controller for a digital video communications channel, the controller comprising:

detector logic for detecting any difference between the number of addresses in the FIFO memory into which data is written and the number of addresses in the FIFO memory from which data is read;

comparator logic for generating a request data transfer signal in response to said difference becoming greater than or equal to a threshold; and

threshold select logic responsive to video data having at least an active line portion and a control portion being written to the FIFO memory, the threshold select logic setting the threshold to a first value when the active line portion is being written and setting the threshold to a second value, greater than the first value, when the control portion is being written.

2. A controller as claimed in claim 1, wherein the threshold select logic comprises:

a control signal generator for generating a binary control signal in response to the video data being written to the FIFO memory, the control signal generator setting the control signal to a first level when the active line portion is being written and setting the control signal to a second level when the control portion is being written; and

a demultiplexer for connecting a first register storing the first value to the comparator logic when the control signal is set to the first level and connecting a second register storing the second value to the comparator logic when the control signal is set to the second level.

3. A controller as claimed in claim 2, wherein the control signal generator comprises:

a counter having a parallel output for counting addresses in the FIFO memory into which video data is being written;

a first decoder connected to the parallel output for generating a first pulse in response to a first output count;

a second decoder connected to the parallel output for generating a second pulse in response to a second output count, the second output count being greater than the first; and

a bistable latch connected to the first and second decoders for setting the control signal to the first level in response to the first pulse and setting the control signal to the second level in response to the second pulse.

4. A controller as claimed in claim 1, wherein the detector logic comprises:

an up/down counter having a parallel output;

a count up clock input for incrementing the parallel output in response to video data being written in address in the FIFO memory; and

a count down clock for decrementing the parallel output in response to video data being read from an address in the FIFO memory.

5. A controller as claimed in claim 1, wherein the detector logic comprises subtractor logic for subtracting a write address stored in a write address pointer connected to the FIFO memory from a read address stored in a read address pointer connected to the FIFO memory.

6. A controller as claimed in claim 1, wherein the first value is set to unity.