Systems and methods for FDC error detection and prevention

• US 5,379,414 A
• Filed: 07/10/1992
• Issued: 01/03/1995
• Est. Priority Date: 07/10/1992
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Phillip M. Adams
• Inventors: Adams, Phillip M.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US07/911,409
• Time in Patent Office: 907 Days
• Field of Search: 371/62, 371/8.2, 371/9.1, 371/11.1, 371/11.3, 371/21.1, 371/28, 371/21.6, 371/37.1, 371/40.1, 371/68.1, 371/66, 371/32, 371/33, 371/34, 371/35, 371/48, 380/4, 380/24, 380/25, 395/425, 395/575, 395/400, 395/375, 395/550, 395/275
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1612 where the redundant component is persistent storage
• CPC Class Codes: G06F 11/3485 for I/O devices
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 20/1816 Testing
• CPC Class Codes: G11B 27/36 Monitoring, i.e. supervising the progress of recording or reproducing for digital recording G11B20/00 and s.gr.; for monitoring, testing or measuring of TV recorders of the type covered by H04N5/76 and subgroups, see H04N17/06

Abstract

A system and method which provides a complete software implementation of a device driver that is capable of detecting an undetectable data corruption problem without hardware redesign and/or internal modification to an existing FDC. The approach taken consists of software DMA shadowing and use of a software decoding network which allows the implementation of the invention to require a small amount of memory and only degrade the performance of the computer system a minimal amount when floppy diskette write operations occur.

Claims

1. A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having:

a central processing unit (CPU);

a system interrupt timer;

a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes;

a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette;

means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and

means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count,

the method comprising the steps of;

determining if a requested computer system operation is a floppy diskette write operation;

reading the data transfer byte count provided by said counting means;

monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette;

measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette; and

forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value.

3. A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 wherein said means for counting data bytes comprises a data transfer count register of a direct memory access (DMA) controller and wherein the reading step comprises reading the DMA controller'"'"'s data transfer count register.

4. A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 further comprising the step of hooking an interrupt vector and directing it to an interposer routine.

5. A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 further comprising the step of reprogramming the system interrupt timer to interrupt faster than normal.

2. A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having:

a central processing unit (CPU);

a system interrupt timer;

a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes;

a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette;

means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and

means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count,

the method comprising the steps of;

determining if a requested computer system operation is a floppy diskette write operation;

hooking an interrupt vector and directing it to an interposer routine;

reprogramming the system interrupt timer to interrupt faster than normal;

installing and calling a software decoding network call vector;

reading the data transfer byte count provided by said counting means;

monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette;

measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette;

forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value;

reprogramming the system interrupt timer to interrupt normally; and

unhooking said interrupt vector.

7. A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 2 wherein said means for counting data bytes comprises a data transfer count register of a direct memory access (DMA) controller and wherein the reading step comprises reading the DMA controller'"'"'s data transfer count register.

6. A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim further comprising the step of installing and calling a software decoding network call vector.