Hermetic semiconductor device having jumper leads

• US 5,381,039 A
• Filed: 05/06/1994
• Issued: 01/10/1995
• Est. Priority Date: 02/01/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Morrison, Paul-David
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US08/239,169
• Time in Patent Office: 249 Days
• Field of Search: 257/668, 257/700, 257/701, 257/704, 257/784, 257/686, 257/778
• US Class Current: 257/701
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/49555 : the bent parts being the outer leads
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20653 : larger or equal to 2500 microns less than 3000 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns

Abstract

A fine-pitch hermetic device (10) can be manufactured wherein two sets of wire bonds (18 & 20) are used to electrically connect a semiconductor die (12) to a leadframe (16). Jumper leads or conductive pads (28) are placed on an inner surface of a ceramic base (14) to electrically interconnect the two sets of wire bonds. The jumper leads enables shorter wire lengths to be used. The leadframe is attached to the ceramic base with glass embed technology. A cap (22) is affixed to the base with a hermetic seal (24). The invention is also compatible with flip-chip dice and multichip modules.

Claims

1. A hermetic semiconductor device comprising:

a ceramic base having a first array of conductive pads on a surface and a second array of conductive pads around a periphery of the first array, wherein the first and second arrays of conductive pads are electrically interconnected by means for routing in the ceramic base;

a leadframe having a plurality of conductors in a quadrilateral configuration, wherein the plurality of conductors is attached to a periphery of the ceramic base with a glass material, the plurality of conductors having a surface mountable external portion that is curved;

a semiconductor die electrically connected to the first array of conductive pads by way of flip-chip bonding with a plurality of conductive interconnect bumps;

a plurality of wire bonds connecting the plurality of conductors to the second array of conductive pads to electrically connect the semiconductor die to the leadframe;

a cap overlying the semiconductor die and substantially aligning with the ceramic base; and

a seal which adhesively couples the ceramic base to the cap to provide a hermetic seal around the semiconductor die.

2. The device of claim 1, wherein the ceramic base further comprises a third array of conductive pads on a second surface of the ceramic base, the third array of conductive pads being electrically connected to the first and second arrays of conductive pads.

3. The device of claim 2 further comprising:

a second ceramic base having a fourth array of conductive pads on a first surface of the second ceramic base and a fifth array of conductive pads on a second surface, wherein the fourth and fifth arrays of conductive pads are electrically interconnected by means for routing in the second ceramic base;

a second semiconductor die electrically connected to the fourth array of conductive pads by way of flip-chip bonding with a second plurality of conductive interconnect bumps;

a second cap overlying the second semiconductor die and substantially aligning with the second ceramic base;

a second seal which adhesively couples the second ceramic base to the second cap to provide a hermetic seal around the second semiconductor die; and

a plurality of solder balls coupling the third array of conductive pads on the second surface of the first ceramic base to the fifth array of conductive pads on the second surface of the second ceramic base, wherein a stacked hermetic semiconductor device is formed.

4. The device of claim 3, wherein the first and second ceramic bases have a cavity for receiving the semiconductor die.

5. The device of claim 3, wherein the first and second seal comprise a material selected from a group consisting of:

glass and solder.

6. The device of claim 3, wherein the first and second cap comprise a material selected from a group consisting of:

ceramic, metal, and alumina.

7. The device of claim 2 further comprising:

a second ceramic base having a fourth array of conductive pads on a first surface of the second ceramic base and a fifth array of conductive pads around a periphery of the fourth array, wherein the fourth and fifth arrays of conductive pads are electrically interconnected by means for routing in the second ceramic base;

a second semiconductor die electrically connected to the fourth array of conductive pads by way of flip-chip bonding with a second plurality of conductive interconnect bumps;

a second leadframe having a second plurality of conductors, wherein the second plurality of conductors is attached to a periphery of the second ceramic base with a glass material, the second plurality of conductors having a surface mountable external portion that is curved;

a second plurality of wire bonds connecting the second plurality of conductors to the fifth array of conductive pads to electrically connect the second semiconductor die to the second leadframe;

a second cap overlying the second semiconductor die and substantially aligning with the second ceramic base; and

a second seal which adhesively couples the second multilayer ceramic base to the second cap to provide a hermetic seal around the second semiconductor die;

wherein the external portion of the second plurality of conductors is physically and electrically connected to the third array of conductive pads to form a stacked hermetic semiconductor device.

8. The device of claim 7, wherein the first and second seal comprise a material selected from a group consisting of:

glass and solder.

9. The device of claim 7, wherein the first and second cap comprise a material selected from a group consisting of:

ceramic, metal, and alumina.

10. A hermetic semiconductor device comprising:

a multilayer ceramic base having a first array of conductive pads on a surface and a second array of conductive pads around a periphery of the first array, wherein the first and second arrays of conductive pads are electrically interconnected by means for routing in the multilayer ceramic base;

a leadframe having a plurality of conductors in a quadrilateral configuration, wherein an inner portion of the plurality of conductors is attached to a periphery of the multilayer ceramic base with a glass material and an outer portion of the plurality of conductors is shaped to a surface mountable configuration;

a semiconductor die electrically connected to the first array of conductive pads by way of flip-chip bonding with a plurality of conductive interconnect bumps;

a plurality of wire bonds connecting the plurality of conductors to the second array of conductive pads to electrically connect the semiconductor die to the leadframe;

a cap overlying the semiconductor die and substantially aligning with the multilayer ceramic base; and

a glass seal which adhesively couples the multilayer ceramic base to the cap to provide a hermetic seal around the semiconductor die.

11. The device of claim 10, wherein the multilayer ceramic base further comprises a third array of conductive pads on a second surface of the multilayer ceramic base, the third array of conductive pads being electrically connected to the first and second arrays of conductive pads.

12. The device of claim 11 further comprising:

a second multilayer ceramic base having a fourth array of conductive pads on a first surface of the second multilayer ceramic base and a fifth array of conductive pads on a second surface, wherein the fourth and fifth arrays of conductive pads are electrically interconnected;

a second semiconductor die electrically connected to the fourth array of conductive pads by way of flip-chip bonding with a second plurality of conductive interconnect bumps;

a second cap overlying the second semiconductor die and substantially aligning with the second multilayer ceramic base;

a second seal which adhesively couples the second multilayer ceramic base to the second cap to provide a hermetic seal around the second semiconductor die; and

a plurality of solder balls coupling the third array of conductive pads on the second surface of the first multilayer ceramic base to the fifth array of conductive pads on the second surface of the second multilayer ceramic base, wherein a stacked hermetic semiconductor device is formed.

13. The device of claim 12, wherein the first and second multilayer ceramic bases have a cavity for receiving the semiconductor die.

14. The device of claim 12, wherein the first and second cap comprise a material selected from a group consisting of:

ceramic, metal, and alumina.

15. The device of claim 11 further comprising:

a second multilayer ceramic base having a fourth array of conductive pads on a first surface of the second multilayer ceramic base and a fifth array of conductive pads around a periphery of the fourth array, wherein the fourth and fifth arrays of conductive pads are electrically interconnected by means for routing in the second multilayer ceramic base;

a second semiconductor die electrically connected to the fourth array of conductive pads by way of flip-chip bonding with a second plurality of conductive interconnect bumps;

a second leadframe having a second plurality of conductors, wherein an inner portion of the second plurality of conductors is attached to a periphery of the second multilayer ceramic base with a glass material, the second plurality of conductors having a surface mountable external portion that is curved;

a second plurality of wire bonds connecting the second plurality of conductors to the fifth array of conductive pads to electrically connect the second semiconductor die to the second leadframe;

a second cap overlying the second semiconductor die and substantially aligning with the second multilayer ceramic base; and

a second seal which adhesively couples the second multilayer ceramic base to the second cap to provide a hermetic seal around the second semiconductor die;

wherein the external portion of the second plurality of conductors is physically and electrically connected to the third array of conductive pads to form a stacked hermetic semiconductor device.

16. The device of claim 15, wherein the first and second cap comprise a material selected from a group consisting of:

ceramic, metal, and alumina.