Fully differential line driver circuit having common-mode feedback

• US 5,381,112 A
• Filed: 09/22/1993
• Issued: 01/10/1995
• Est. Priority Date: 09/22/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Brooks, Todd L., Rybicki, Mathew A.
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): DUDEK, JAMES A
• Application Number:
  US08/124,684
• Time in Patent Office: 475 Days
• Field of Search: 365/230.06, 365/189.11, 365/189.09, 307/270, 330/258, 330/295, 330/311, 330/84, 330/255, 330/253, 330/260
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45408 the CMCL comprising a short circuited differential output of a dif amp as an addition circuit
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45424 the CMCL comprising a comparator circuit
• CPC Class Codes: H03F 3/45112 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45121 Folded cascode stages
• CPC Class Codes: H03F 3/45654 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03F 3/45717 Controlling the loading circuit of the differential amplifier

Abstract

A fully differential line driver circuit (25) includes an input differential amplifier (26) and double-ended differential amplifiers (27, 28). A first output driver stage (29) includes a pair of series connected transistors (30, 31), and a second output driver stage includes a pair of series connected transistors (33, 34). The differential amplifiers (27, 28) provide bias and signals voltages to the gates of the series connected transistors (30, 31, 33, 34). The output stages (29, 32) provide differential output signals for driving a low impedance load. The clamping circuits (35-38) control overlap currents in the output stages (29, 32). Common-mode feedback is used to ensure a common-mode voltage of the differential output signals remains at a predetermined voltage to ensure maximum signal swing and thus, maximum efficiency.

Claims

1. A line driver circuit, comprising:

a first differential amplifier having first and second input terminals for receiving first and second input signals, and having first and second output terminals for providing first and second intermediate signals;

a first common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the first differential amplifier, respectively, for sensing a common-mode voltage of the first and second input signals, and controlling a common-mode voltage of the first and second intermediate signals;

a second differential amplifier having first and second input terminals for receiving the first and second input signals, and having first and second output terminals for providing third and fourth intermediate signals;

a second common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the second differential amplifier, respectively, for sensing the common-mode voltage of the first and second input signals, and controlling a common-mode voltage of the third and fourth intermediate signals;

a first output driver stage having first and second transistors coupled in series for receiving the first intermediate signal and the third intermediate signal, and for providing a first output signal at a first output node between the first and second transistors; and

a second output driver stage having third and fourth transistors coupled in series for receiving the second intermediate signal and the fourth intermediate signal, and for providing a second output signal at a second output node between the third and fourth transistors.

2. The line driver circuit of claim 1, further comprising:

a first clamping circuit, coupled to the first output driver stage, for controlling an overlap current in the first and second transistors when the first and second output signals are in a cross-over region; and

a second clamping circuit, coupled to the second output driver stage, for controlling an overlap current in the third and fourth transistors when the first and second output signals are in the cross-over region.

3. The line driver circuit of claim 1, wherein the first and second output signals are characterized as being differential output signals.

4. The line driver circuit of claim 3, further comprising an input differential amplifier having first and second input terminals for receiving differential input signals, and first and second output terminals coupled to the input terminals of the first and second differential amplifiers, for providing the first and second input signals.

5. The line driver circuit of claim 4, further comprising a common mode feedback circuit, coupled to the input differential amplifier and to the first and second output nodes, for sensing a common-mode voltage of the first and second output signals and providing a common-mode feedback voltage to ensure that the common-mode voltage of the first and second output signals is provided at a predetermined voltage level.

6. The line driver circuit of claim 5, wherein the common-mode feedback circuit further comprises a voltage divider circuit for sensing the common-mode voltage of the first and second output signals.

7. The line driver circuit of claim 5, wherein the common-mode feedback circuit comprises:

a first common-mode feedback circuit for sensing the common-mode voltage of the first and second output signals, and providing a first common-mode feedback voltage to ensure that a common-mode voltage of the first and second input signals is provided at a predetermined voltage level; and

a second common-mode feedback circuit for sensing a common-mode voltage of the first and second input signals and providing a second common-mode feedback voltage to ensure that a common-mode voltage of the first and second output signals are provided at the predetermined voltage level.

8. The line driver circuit of claim 7, wherein the predetermined voltage level is equal to substantially one-half of a power supply voltage.

9. The line driver circuit of claim 1, further comprising:

a first compensation capacitor having a first plate electrode coupled to the first input terminals of the first and second differential amplifiers, and a second plate electrode coupled to the first output node; and

a second compensation capacitor having a first plate electrode coupled to the second input terminals of the first and second differential amplifiers, and a second plate electrode coupled to the second output node.

10. A CMOS differential line driver circuit, comprising:

an input differential amplifier having first and second input terminals for receiving differential input signals, and first and second output terminals for providing first and second intermediate differential signals;

a first differential amplifier having first and second input terminals coupled to the first and second output terminals of the input differential amplifier, and having first and second output terminals for providing third and fourth intermediate signals;

a first common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the first differential amplifier, respectively, for sensing a common-mode voltage of the first and second intermediate signals, and controlling a common-mode voltage of the third and fourth intermediate signals;

a second differential amplifier having first and second input terminals coupled to the first and second output terminals of the input differential amplifier, and having output terminals for providing fifth and sixth intermediate signals;

a second common-mode control circuit having first and second input terminals coupled to the first and second input terminals of the second differential amplifier, respectively, for sensing the common-mode voltage of the first and second intermediate Signals, and controlling a common-mode voltage of the fifth and sixth intermediate signals;

a first output driver stage having first and second transistors coupled in series for receiving the third intermediate signal and the fifth intermediate signal, and for providing a first output signal at a first output node between the first and second transistors;

a second output driver stage having third and fourth transistors coupled in series for receiving the fourth intermediate signal and the sixth intermediate signal, and for providing a second output signal at a second output node between the third and fourth transistors; and

a common-mode feedback circuit, coupled to the first and second output nodes and to the input differential amplifier, for sensing a common-mode voltage of the first and second output signals, and providing a common-mode feedback voltage to control the common-mode voltage of the first and second intermediate signals.

11. The line driver circuit of claim 10;

wherein the common-mode feedback circuit comprises;

a voltage divider circuit for sensing the common-mode voltage of the first and second output signals; and

a third differential amplifier for comparing the common-mode feedback voltage to a reference voltage.

12. The line driver circuit of claim 10, further comprising:

a first compensation capacitor having a first plate electrode coupled to the first input terminals of the first and second differential amplifiers, and a second plate electrode coupled to the first output node; and

a second compensation capacitor having a first plate electrode coupled to the second input terminals of the first and second differential amplifiers, and a second plate electrode coupled to the second output node.

13. The line driver circuit of claim 10, further comprising:

a first clamping circuit, coupled to the first output driver stage, for controlling an overlap current in the first and second transistors when the first and second output signals are in a cross-over region; and

a second clamping circuit, coupled to the second output driver stage, for controlling an overlap current in the third and fourth transistors when the first and second output signals are in the cross-over region.

14. A fully differential line driver circuit, comprising:

a high gain input amplifier stage having first and second input terminals for receiving first and second input signals, respectively, and first and second output terminals for providing first and second intermediate differential signals;

a first differential amplifier, comprising;

a first P-channel transistor having a source connected to a first power supply voltage terminal, a gate, and a drain;

a second P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the gate of the first P-channel transistor, and a drain;

a first N-channel transistor having a drain connected to the drain of the first P-channel transistor, a gate connected to the first output terminal of the high gain input amplifier stage, and a source;

a second N-channel transistor having a drain connected to the drain of the second P-channel transistor, a gate connected to the second output terminal of the high gain input amplifier stage, and a source connected to the source of the first N-channel transistor; and

a first current source having a first terminal connected to the sources of the first and second N-channel transistors, and a second terminal connected to a second power supply voltage terminal;

a second differential amplifier comprising;

a third N-channel transistor having a source connected to the second power supply voltage terminal, a gate, and a drain;

a fourth N-channel transistor having a source connected to the second power supply voltage terminal, a gate connected to the gate of the third N-channel transistor, and a drain;

a third P-channel transistor having a drain connected to the drain of the third N-channel transistor, a gate connected to the first output terminal of the high gain input amplifier stage, and a source;

a fourth P-channel transistor having a drain connected to the drain of the fourth N-channel transistor, a gate connected to the second output terminal of the high gain input amplifier stage, and a source connected to the source of the third P-channel transistor; and

a second current source having a first terminal connected to the first power supply voltage terminal, and a second terminal connected to the sources of the third and fourth P-channel transistors;

a first output stage, comprising;

a fifth P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the drain of the first P-channel transistor, and a drain for providing a first output signal; and

a fifth N-channel transistor having a drain connected to the drain of the fifth P-channel transistor, a gate connected to the drain of the third P-channel transistor, and a source connected to the second power supply voltage terminal; and

a second output stage, comprising;

a sixth P-channel transistor having a source connected to the first power supply voltage terminal, a gate connected to the drain of the second P-channel transistor, and a drain for providing a second output signal; and

a sixth N-channel transistor having a drain connected to the drain of the sixth P-channel transistor, a gate connected to the drain of the fourth P-channel transistor, and a source connected to the second power supply voltage terminal.

15. The fully differential line driver circuit of claim 14, wherein the high gain input amplifier stage comprises:

a third current source having a first terminal connected to the first power supply voltage terminal, and a second terminal;

a seventh P-channel transistor having a source connected to the second terminal of the third current source, a gate for receiving the first input signal, and a drain;

an eighth P-channel transistor having a source connected to the second terminal of the third current source, a gate for receiving the second input signal, and a drain;

a seventh N-channel transistor having a drain connected to the drain of the seventh P-channel transistor, a gate, and a source connected to the second power supply voltage terminal;

an eighth N-channel transistor having a drain connected to the drain of the eighth P-channel transistor, a gate connected to the gate of the seventh N-channel transistor, and a source connected to the second power supply voltage terminal;

a fourth current source having a first terminal connected to the second power supply,voltage terminal, and a second terminal;

a ninth N-channel transistor having a source connected to the second terminal of the fourth current source, a gate for receiving the first input signal, and a drain;

a tenth N-channel transistor having a source connected to the second terminal of the fourth current source, a gate for receiving the second input signal, and a drain;

a fifth current source having a first terminal connected to the first power supply voltage terminal, and a second terminal connected to the drain of the ninth N-channel transistor;

a sixth current source having a first terminal connected to the first power supply voltage terminal, and a second terminal connected to the drain of the tenth N-channel transistor;

a ninth P-channel transistor having a source connected to the second terminal of the fifth current source, a gate for receiving a first bias voltage, and a drain connected to the gates of both of the first N-channel transistor and the third P-channel transistor;

a tenth P-channel transistor having a source connected to the second terminal of the sixth current source, a gate for receiving the first bias voltage, and a drain connected to the gates of both of the second N-channel transistor and the fourth P-channel transistor;

an eleventh N-channel transistor having a drain connected to the drain of the ninth P-channel transistor, a gate for receiving a second bias voltage, and a source connected to the drain of seventh N-channel transistor; and

a twelfth N-channel transistor having a drain connected to the drain of the tenth P-channel transistor, a gate for receiving the second bias voltage, and a source connected to the drain of the eighth N-channel transistor.

16. The fully differential line driver circuit of claim 15, further comprising:

a voltage divider circuit having a first terminal connected to the drain of the fifth P-channel transistor, and a second terminal connected to the drain of the sixth P-channel transistor;

a common-mode feedback circuit having a first input terminal connected to the voltage divider circuit, a second input terminal for receiving a reference voltage, and an output terminal connected to the gates of the seventh and eighth N-channel transistors;

a first common-mode control circuit having a first input terminal connected to the gate of the first N-channel transistor, a second input terminal connected to the gate of the second N-channel transistor, and an output terminal connected to the gates of the first and second P-channel transistors; and

a second common-mode control circuit having a first input terminal connected to the gate of the third P-channel transistor, a second input terminal connected to the gate of the fourth P-channel transistor, and an output terminal connected to the gates of the third and fourth N-channel transistors.

17. The fully differential line driver circuit of claim 15, further comprising:

a first common-mode feedback circuit having a first input terminal connected to the drain of the tenth P-channel transistor, a second input terminal connected to the drain of the ninth P-channel transistor, and an output terminal connected to the gates of the seventh and eighth N-channel transistors;

a voltage divider circuit having a first terminal connected to the drain of the fifth P-channel transistor, and a second terminal connected to the drain of the sixth P-channel transistor;

a second common-mode feedback circuit having a first input terminal connected to the voltage divider circuit, a second input terminal for receiving a reference voltage, and an output terminal connected to the gates of the first and second P-channel transistors; and

a third common-mode feedback circuit having a first input terminal connected to the voltage divider circuit, a second input terminal for receiving the reference voltage, and an output terminal connected to the gates of the third and fourth N-channel transistors.

18. The fully differential line driver circuit of claim 15, further comprising:

a first voltage divider circuit having a first terminal connected to the drain of the fifth P-channel transistor, and a second terminal connected to the drain of the sixth P-channel transistor;

a first common-mode feedback circuit having a first input terminal connected to the first voltage divider circuit, a second input terminal for receiving a reference voltage, and an output terminal connected to the gates of the seventh and eighth N-channel transistors;

a second voltage divider circuit having a first terminal connected to the drain of the ninth P-channel transistor, and a second terminal connected to the drain of the tenth P-channel transistor;

a second common-mode feedback circuit having a first input terminal connected to the second voltage divider circuit, a second input terminal for receiving the reference voltage, and an output terminal connected to the gates of the first and second P-channel transistors; and

a third common-mode feedback circuit having a first input terminal connected to the second voltage divider circuit, a second input terminal for receiving the reference voltage, and an output terminal connected to the gates of the third and fourth N-channel transistors.

19. The fully differential line driver circuit of claim 14, further comprising:

a first clamping circuit, coupled to the gate of the fifth P-channel transistor and a second clamping circuit coupled to the gate of the fifth N-channel transistor, for controlling an overlap current in the fifth P-channel transistor and in the fifth N-channel transistor; and

a third clamping circuit, coupled to the gate of the sixth P-channel transistor and a fourth clamping circuit coupled to the gate of the sixth N-channel transistor, for controlling an overlap current in the sixth P-channel transistor and in the sixth N-channel transistor.

20. The fully differential line driver circuit of claim 14, further comprising:

a first compensation capacitor having a first plate electrode connected to the gate of the fourth P-channel transistor, and a second plate electrode connected to the drain of the fifth P-channel transistor; and

a second compensation capacitor having a first plate electrode connected to the gate of the third P-channel transistor, and a second plate electrode connected to the drain of the sixth P-channel transistor.