Fast static cross-unit comparator

• US 5,381,127 A
• Filed: 12/22/1993
• Issued: 01/10/1995
• Est. Priority Date: 12/22/1993
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Khieu, Cong Q.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US08/172,424
• Time in Patent Office: 384 Days
• Field of Search: 340/146.2
• US Class Current: 340/146.2
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A high speed, static, BiCMOS comparator circuit. Though static, the circuit operates at nearly dynamic speeds. The circuit consists of two stages. The first stage generates XOR and XNOR outputs given two bit strings. The second stage detects hit and miss separately using the XOR and XNOR inputs. The second stage generates signals for both hit lines and miss lines.

Claims

1. A static comparator circuit capable of operating at high speeds while consuming very little power, said comparator circuit comprising:

a first stage accepting a first bit string and a second bit string, said first stage generating a first output, said first output comprising a plurality of voltages corresponding to an XOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string, said first stage also generating a second output, said second output comprising a plurality of voltages corresponding to an XNOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string; and

a second stage comprising a hit-miss detection circuit, said hit-miss detection circuit comprising a hit line and a miss line, said hit-miss detection circuit further comprising NMOS transistors having NMOS transistor gates and PMOS transistors having PMOS transistor gates, each of said NMOS transistor gates and each of said PMOS transistor gates being controlled by each of said first plurality of voltages and each of said second plurality of voltages respectively, said NMOS transistors being connected in parallel to each other and said PMOS transistors being connected in parallel to each other such that when any one of said NMOS transistor gates goes high and any one of said PMOS transistor gates goes low, said hit line is pulled down and said miss line is pulled up.

2. The comparator circuit of claim 1 wherein said hit-miss detection circuit further comprises a first bipolar transistor whose emitter is coupled to said miss line for use in pulling up said miss line.

3. The comparator circuit of claim 2 further comprising protection circuitry for raising a base voltage appearing at a base of said first bipolar transistor from a low base voltage to a higher base voltage when an emitter voltage appearing at an emitter of said first bipolar transistor switches from a low emitter voltage to a high emitter voltage thereby reducing or eliminating a reverse bias voltage appearing across a base-emitter junction of said first bipolar transistor.

4. The comparator circuit of claim 2 further comprising circuitry to provide approximately full voltage swing on said miss line.

5. The comparator circuit of claim 1 wherein said hit-miss detection circuit further comprises a second bipolar transistor whose collector is coupled to said hit line for use in pulling down said hit line.

6. The comparator circuit of claim 5 further comprising circuitry to pull said hit line up to approximately Vdd.

7. The comparator circuit of claim 1 wherein said hit line is at least partially charged high by a static charge-up, MOS transistor.

8. The comparator circuit of claim 1 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

9. The comparator circuit of claim 3 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

10. The comparator circuit of claim 6 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

11. The comparator circuit of claim 1 wherein said comparator circuit is used to determine if a probe tag differs from a stored tag in a memory system.

12. A computer system comprising:

a memory for storage of information;

a processor coupled to said memory for manipulation of said information;

said processor including a comparator circuit;

said comparator circuit comprising a first stage accepting a first bit string and a second bit string, said first stage generating a first output, said first output comprising a first plurality of voltages corresponding to an XOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string, said first stage also generating a second output, said second output comprising a second plurality of voltages corresponding to an XNOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string; and

said comparator circuit additionally including a second stage, said second stage comprising a hit-miss detection circuit, said hit-miss detection circuit comprising a hit line and a miss line, said hit-miss detection circuit further comprising NMOS transistors having NMOS transistor gates and PMOS transistors having PMOS transistor gates, each of said NMOS transistor gates and each of said PMOS transistor gates being controlled by voltages corresponding to each of said first plurality of voltages and each of said second plurality of voltages respectively, said NMOS transistors being connected in parallel to each other and said PMOS transistors being connected in parallel to each other such that when any one of said NMOS transistor gates goes high and any one of said PMOS transistor gates goes low, said hit line is pulled down and said miss line is pulled up.

13. The computer system of claim 12 wherein said hit-miss detection circuit further comprises a first bipolar transistor whose emitter is coupled to said miss line for use in pulling up said miss line.

14. The computer system of claim 13 further comprising protection circuitry for raising a base voltage appearing at a base of said first bipolar transistor from a low base voltage to a higher base voltage when an emitter voltage appearing at an emitter of said first bipolar transistor switches from a low emitter voltage to a high emitter voltage thereby reducing or eliminating a reverse bias voltage appearing across a base-emitter junction of said first bipolar transistor.

15. The computer system of claim 13 further comprising circuitry to provide approximately full voltage swing on said miss line.

16. The computer system of claim 12 wherein said hit-miss detection circuit further comprises a second bipolar transistor whose collector is coupled to said hit line for use in pulling down said hit line.

17. The computer system of claim 16 further comprising circuitry to pull said hit line up to approximately Vdd.

18. The computer system of claim 12 wherein said hit line is at least partially charged high by a static charge-up, MOS transistor.

19. The computer system of claim 12 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

20. The computer system of claim 14 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

21. The computer system of claim 17 wherein said second stage comprises a plurality of said hit-miss detection circuits, each of said hit-miss detection circuits accepting different portions of said first plurality of voltages and said second plurality of voltages.

22. The computer system of claim 12 wherein said comparator circuit is used to determine if a probe tag differs from a stored tag in said memory.

23. A method of comparing a first bit string to a second bit string to determine if they are the same, said method comprising:

generating a first plurality of voltages corresponding to an XOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string;

generating a second plurality of voltages corresponding to an XNOR function applied to at least a portion of said first bit string and an equivalent portion of said second bit string; and

generating a hit signal and a miss signal on a hit line and a miss line, respectively, by controlling each of a plurality of gates of a plurality of NMOS transistors using each of said first plurality of voltages and controlling each of a plurality of gates of a plurality of PMOS transistors using each of said second plurality of voltages, said plurality of NMOS transistors being connected in parallel to each other and said plurality of PMOS transistors being connected in parallel to each other such that when any one of said NMOS transistor gates goes high and any one of said PMOS transistor gates goes low, said hit line is pulled down and said miss line is pulled up.