Semiconductor device with low thermally generated leakage current

• US 5,382,814 A
• Filed: 08/12/1993
• Issued: 01/17/1995
• Est. Priority Date: 01/08/1991
• Status: Expired due to Term

• Current Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Original Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Inventors: Ashley, Timothy, Elliott, Charles T., Whitehouse, Colin R.
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/084,280
• Time in Patent Office: 523 Days
• Field of Search: 257/183, 257/183.1, 257/184, 257/82, 257/197, 257/192, 257/196, 257/198, 257/199
• US Class Current: 257/197
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor device in the form of a metal insulator field effect transistor (MISFET) (200) is constructed as a heterostructure of narrow bandgap In_1-x Al_x Sb semiconductor materials. The MISFET (200) is formed from four semiconducting layers (112 to 118) arranged in series as follows: a heavily doped p-type first layer (112), a heavily doped relatively wider bandgap p-type second layer (114), a lightly doped p-type third layer (116) and a heavily doped n-type fourth layer (118). A source (202) and a drain (204) are formed in the fourth layer (118) and a gate (116/205) in the third layer. An n⁺ p^- junction (124) is formed between the third and fourth layers and a p⁺ p^- junction (122) between the second and third layers. The second layer (114) provides a conduction band potential energy barrier to minority carrier (electron) flow to the gate (116/205), and is sufficiently wide to prevent tunnelling of minority carriers therebetween. The first and second layers (112, 114) in combination provide a p⁺ p⁺ excluding contact to the third layer (116). The n⁺ p^- junction (124) between the third and fourth layers (116, 118) is an extracting contact; when reverse biased in operation, this junction (124) extracts minority carriers from the region of the third layer (116) adjacent the collector (118/204). In operation, the third layer (116) incorporating the gate (205) becomes depleted of charge carriers and therefore exhibits greatly reduced leakage current. In consequence, the MISFET (200) has good dynamic range in terms of controllable drain current. The invention also provides bipolar transistors (300, 400 ) and related devices.

Claims

1. A semiconductor device having first, second and third semiconducting region connected in series for current input, current control and current output respectively and each arranged to be biased by a respective biasing means, wherein the device includes an extracting contact comprising a means for extracting minority carriers from the second region and the second region is of low doping and has a common interface with a fourth semiconducting region, said fourth semiconducting region having a common interface with a fifth semiconducting region, and wherein the fourth region:

(a) has like majority carrier type to that of the fifth region,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the second region adjacent the third region and thereby to reduce the intrinsic contribution to current reaching the third region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the second region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the second region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the second region.

2. A device according to claim 1 wherein it is a field effect transistor in which the first, second and third regions are source, gate and drain regions respectively, and the first and third regions are of like majority carrier type opposite to that of the fourth and fifth regions.

3. A device according to claim 2 wherein it is an enhancement mode field effect transistor in which the second region is of like majority carrier type to that of the fourth and fifth regions.

4. A device according to claim 3 wherein the second region is a layer having first and second sides separated by the layer thickness, the first and third regions are connected to the first side of the second region, the fourth region is connected to the second side of the second region and the fifth region is connected to a side of the fourth region remote from the first, second and third regions.

5. A device according to claim 4 wherein the fourth region is connected to the second region over an area at least as extensive and correspondingly located as those parts of the second region adjacent and between the first and third regions, the fourth region being arranged to provide minority carrier exclusion over most or all of the second region.

9. A device according to claim 1 wherein it is formed from a series of layers disposed successively on a common substrate, the fifth region being a first layer supported by the substrate, the fourth region being a second layer in contact with the fifth layer, the second region being a third layer in contact with the second layer, and the first and third regions being formed from a common fourth layer in contact with the third layer.

10. A device according to claim 1 wherein said device is a bipolar transistor in which the first, second and third regions are emitter, base and collector regions respectively, the first and third regions are of like majority carrier type opposite to that of the second, fourth and fifth regions, and the fourth region comprises a means for providing minority carrier exclusion effects over substantially all of the second region.

14. A device according to claim 10 wherein the fourth region bandgap is at least 3 kT/q Volts wider than at least one of said second region and said fifth region, where q is the electronic charge, k is Boltzmann'"'"'s constant and T is the device operating temperature.

15. A device according to claim 10 wherein:

(a) the first region and the third region are of InSb having an n-type dopant concentration of at least 2×

10¹⁷ atoms/cm³,

(b) the second region is of InSb having a p-type dopant concentration of less than l×

10¹⁷ atoms/cm³, and

(c) the fourth region is of In_1-x Al_x Sb having a p-type dopant concentration of at least 5×

10¹⁷ atoms/cm³, where x is a compositional parameter in the range 0.01 to 0.7, and

(d) the fifth region is of InSb with a p-type dopant concentration of at least 5×

10¹⁷ atoms/cm³.

16. A device according to claim 15 wherein the fourth region bandgap is at least 5 kT/q Volts wider than at least one of said second region and said fifth region, where q is the electronic charge, k is Boltzmann'"'"'s constant and T is the device operating temperature.

6. A semiconductor device having first, second and third semiconducting regions connected in series for current input, current control and current output respectively and each arranged to be biased by a respective biasing means, wherein the device includes an extracting contact comprising a means for extracting minority carriers from the second region, and the second region is of low doping and has a common interface with a fourth semiconducting region, said fourth semiconducting region having a common interface with a fifth semiconducting region, and wherein the fourth region:

(a) has like majority carrier type to that of the fifth region,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the second region adjacent the third region and thereby to reduce the intrinsic contribution to current reaching the third region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the second region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the second region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the second region wherein the fourth region bandgap is at least 3 kT/q Volts wider than at least one of said second region and said fifth region, where q is the electronic charge, k is Boltzmann'"'"'s constant and T is the device operating temperature.

7. A semiconductor device having first, second and third semiconducting regions connected in series for current input, current control and current output respectively and each arranged to be biased by a respective biasing means, wherein the device includes an extracting contact comprising a means for extracting minority carriers from the second region, and the second region is of low doping and has a common interface with a fourth semiconducting region, said fourth semiconducting region having a common interface with a fifth semiconducting region, and wherein the fourth region:

(a) has like majority carrier type to that of the fifth region,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the second region adjacent the third region and thereby to reduce the intrinsic contribution to current reaching the third region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the second region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the second region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the second region wherein;

(a) the first and third regions are of InSb having an n-type dopant concentration of at least 2×

10¹⁷ atoms/cm³,

(b) the second region is of InSb having a p-type dopant concentration of less than 1×

10¹⁷ atoms/cm³,

(c) the fourth region is of In_1-x Al_x Sb having a p-type dopant concentration of at least 5×

10¹⁷ atoms/cm³, where x is a compositional parameter in the range 0.01 to 0.7, and

(d) the fifth region is of InSb with a p-type dopant concentration of at least 5×

10¹⁷ atoms/cm³.

8. A device according to claim 7 wherein the fourth region bandgap is at least 5 kT/q Volts wider than at least one of said second region and said fifth region, where q is the electronic charge, k is Boltzmann'"'"'s constant and T is the device operating temperature.

11. A semiconductor device having first, second and third semiconducting regions connected in series for current input, current control and current output respectively and each arranged to be biased by a respective biasing means, wherein the device includes an extracting contact comprising a means for extracting minority carriers from the second region, and the second region is of low doping and has a common interface with a fourth semiconducting region, said fourth semiconducting region having a common interface with a fifth semiconducting region, and wherein the fourth region:

(a) has like majority carrier type to that of the fifth region,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the second region adjacent the third region and thereby to reduce the intrinsic contribution to current reaching the third region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the second region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the second region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the second region;

wherein said device is a bipolar transistor in which the first, second and third regions are emitter, base and collector regions respectively, the first and third regions are of like majority carrier type opposite to that of the second, fourth and fifth regions, and the fourth region is arranged to provide minority carrier exclusion effects over substantially all of the second region wherein the second region is a layer having first and second sides separated by its layer thickness, the first and third regions are connected respectively to the first and second sides of the second region, and the fourth region is connected on one side to the first side of the second region and on the other side to the fifth region.

12. A device according to claim 11 wherein the second region is associated with a further biasing means connected to a different part of the second region to that to which the fourth region is connected, and the further biasing means incorporates semiconducting regions of like composition to those of the fourth and fifth regions.

13. A device according to claim 12 wherein the further biasing means and the fourth region are annular and are both disposed about the first region.

17. A semiconductor device comprising a field effect transistor having semiconducting source, gate and drain regions, and wherein the device includes an extracting contact comprising a means for extracting minority carriers from the gate region, the gate region is of low doping and has a common interface with a fourth semiconducting region, said fourth semiconducting region having a common interface with a fifth semiconducting region, the source and drain regions have like majority carrier type opposite to that of the gate region and the fourth and fifth regions, the source, gate and drain regions and the fourth and fifth regions each being of semiconductor bandgap less than 0.7 eV, and the fourth region:

(a) has like majority carrier type to that of the fifth region,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the gate region adjacent the drain region and thereby to reduce the intrinsic contribution to current reaching the drain region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the gate region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the gate region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the gate region.

18. A semiconductor device comprising a field effect transistor having source, gate and drain regions and incorporating an extracting contact comprising a means for extracting minority carriers from the gate region, and wherein the gate region is a layer of low doping interfaced on one side with the source and drain regions and on another side with a fourth semiconducting region, said fourth semiconducting region interfaced with a fifth semiconducting region separated from the gate region by the fourth region thickness, the source and drain regions are of like majority carrier type, and the fourth region:

(a) has like majority carrier type to that of the fifth region and opposite to that of the source and drain regions,

(b) is biasable through the fifth region and comprises an excluding contact means for excluding minority carriers from at least parts of the gate region adjacent the drain region and thereby to reduce the intrinsic contribution to current reaching the drain region,

(c) has a bandgap sufficiently large to provide a potential energy barrier to minority carrier flow from the fifth region to the gate region,

(d) has sufficiently high doping to counteract potential barrier impediment to majority carrier flow from the gate region to the fifth region, and

(e) is less wide than a critical thickness associated with dislocation formation but sufficiently wide to inhibit tunnelling of minority carriers from the fifth region to the gate region.

19. A device according to claim 18 wherein the fourth region is connected to the gate region over an area at least as extensive and correspondingly located as those parts of the gate region adjacent and between the source and drain regions, the fourth region comprising a means for providing minority carrier exclusion over most of the gate region.