High power field effect transistor
First Claim
1. A field effect transistor comprising:
- an active layer formed in a surface layer of a semiconductor substrate;
a highly doped impurity source region and a highly doped impurity drain region formed in a surface portion of said semiconductor substrate, said active layer being interposed between said source region and said drain region;
a gate electrode formed on said semiconductor substrate, said gate electrode havinga source side edge portion which overlaps said highly doped impurity source region, an insulation film being interposed between said source side edge portion and said highly doped impurity source region, anda drain side edge portion which physically contacts said active layer and which does not extend to said highly doped impurity drain region;
a source electrode formed on said highly doped impurity source region; and
a drain electrode formed on said highly doped impurity drain region.
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Accused Products
Abstract
There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.
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Citations
6 Claims
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1. A field effect transistor comprising:
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an active layer formed in a surface layer of a semiconductor substrate; a highly doped impurity source region and a highly doped impurity drain region formed in a surface portion of said semiconductor substrate, said active layer being interposed between said source region and said drain region; a gate electrode formed on said semiconductor substrate, said gate electrode having a source side edge portion which overlaps said highly doped impurity source region, an insulation film being interposed between said source side edge portion and said highly doped impurity source region, and a drain side edge portion which physically contacts said active layer and which does not extend to said highly doped impurity drain region; a source electrode formed on said highly doped impurity source region; and a drain electrode formed on said highly doped impurity drain region. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification