High power field effect transistor

• US 5,382,821 A
• Filed: 12/14/1992
• Issued: 01/17/1995
• Est. Priority Date: 12/14/1992
• Status: Expired due to Fees

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Nakajima, Shigeru
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Fahmy, Wael M.
• Application Number:
  US07/988,258
• Time in Patent Office: 764 Days
• Field of Search: 257/487, 257/488, 257/401, 257/502, 257/341, 257/192, 257/401, 257/333, 257/334, 257/487, 257/488, 257/341, 257/192, 257/502
• US Class Current: 257/401
• CPC Class Codes: H01L 29/42316 for field-effect transistors

Abstract

There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1_GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.

Claims

1. A field effect transistor comprising:

an active layer formed in a surface layer of a semiconductor substrate;

a highly doped impurity source region and a highly doped impurity drain region formed in a surface portion of said semiconductor substrate, said active layer being interposed between said source region and said drain region;

a gate electrode formed on said semiconductor substrate, said gate electrode having

a source side edge portion which overlaps said highly doped impurity source region, an insulation film being interposed between said source side edge portion and said highly doped impurity source region, and

a drain side edge portion which physically contacts said active layer and which does not extend to said highly doped impurity drain region;

a source electrode formed on said highly doped impurity source region; and

a drain electrode formed on said highly doped impurity drain region.

2. A field effect transistor according to claim 1 wherein a distance between the gate electrode and the highly doped impurity drain region is between 1 μ

m and 5 μ

m, inclusive.

3. A field effect transistor according to claim 2 wherein the insulation film overlaps the active layer.

4. A field effect transistor according to claim 2, wherein said insulation film has an edge portion provided on a source side edge of said active layer.

5. A field effect transistor according to claim 3 wherein the semiconductor substrate is a compound semiconductor substrate.

6. A field effect transistor according to claim 5 wherein the compound semiconductor substrate is a GaAs semiconductor substrate.