Differential voltage follower

• US 5,382,916 A
• Filed: 10/30/1991
• Issued: 01/17/1995
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: King, Ken R., Riemer, David W., Cotreau, Gerald M.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/785,395
• Time in Patent Office: 1,175 Days
• Field of Search: 330/116, 330/253, 330/257, 330/275, 330/288, 330/301
• US Class Current: 330/253
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/505 with field-effect devices
• CPC Class Codes: H03G 1/0082 using bipolar transistor-type devices
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Claims

1. A differential voltage follower, comprising:

(a) a first input node connected to a first load;

(b) a second input node connected to a second load, said second load matched to said first load;

(c) a first follower with input connected to said first input node and with output connected to a control input of both said first and second loads;

(d) a second follower with input connected to said second input node and with output connected to an output node;

(e) wherein said first follower includes a first current mirror and said second follower includes a second current mirror, said first and second current mirrors cross-coupled to tie the currents through said followers.

2. The differential voltage follower of claim 1, wherein:

(a) said first follower includes a first field effect transistor (FET) with gate connected to said first input node and source connected to said first mirror;

(b) said second follower includes a second FET with gate connected to said second input node and source connected to said second mirror;

(c) said first mirror includes a first pair of bipolar transistors (BJTs), the emitters of said first pair of BJTs connected together and forming said first follower output, the bases of said first pair of BJTs connected together, the collector of one of said first pair of BJTs connected to both its base and the source of said first FET, and the collector of the other of said first pair of BJTs connected to the source of said second FET; and

(d) said second mirror includes a second pair of bipolar transistors (BJTs), the emitters of said second pair of BJTs connected together and forming said second follower output, the bases of said second pair of BJTs connected together, the collector of one of said second pair of BJTs connected to both its base and the source of said second FET, and the collector of the other of said second pair of BJTs connected to the source of said first FET.

3. The differential voltage follower of claim 2, wherein:

(a) said FETs are NMOS;

(b) said BJTs are NPN; and

(c) said first and second loads are each an NPN with said control input the base.

4. The differential voltage follower of claim 2, further comprising:

(a) a first current source connected to said output node;

(b) a third current mirror with reference current the current through said second FET and with output current a current through said first follower.

5. The differential voltage follower of claim 1, wherein:

(a) said first follower includes a first field effect transistor (FET) with gate connected to said first input node and source connected to said first mirror;

(b) said second follower includes a second FET with gate connected to said second input node and source connected to said second mirror;

(c) said first mirror includes a first pair of FETs, the sources of said first pair of FETs connected together and forming said first follower output, the gates of said first pair of FETs connected together, the drain of one of said first pair of FETs connected to both its gate and the source of said first FET, and the drain of the other of said first pair of FETs connected to the source of said second FET; and

(d) said second mirror includes a second pair of FETs, the sources of said second pair of FETs connected together and forming said second follower output, the gates of said second pair of FETs connected together, the drain of one of said second pair of FETs connected to both its gate and the source of said second FET, and the drain of the other of said second pair of FETs connected to the source of said first FET.

6. A differential voltage follower, comprising:

(a) first and second input nodes;

(b) first and second field effect transistors with a gate of said first transistor coupled to said first node and a gate of said second transistor coupled to said second node;

(c) third, fourth, fifth, and sixth bipolar transistors cross-coupled with the collectors of said third and sixth bipolars connected to the source of said first field effect transistor and the collectors of said fourth and fifth bipolars connected to the source of said second field effect transistor, said fourth bipolar mirroring the collector current of said third bipolar, and said sixth bipolar mirroring the collector current of said fifth bipolar, whereby the drain current of said first and second field effect transistors is each split between said mirroring bipolars; and

(d) first and second output nodes, said first output node connected to the emitter of said third bipolar and said second output node connected to the emitter of said fifth bipolar.