Capacitance multiplier for the internal frequency compensation of switching regulator integrated circuits

• US 5,382,918 A
• Filed: 02/04/1993
• Issued: 01/17/1995
• Est. Priority Date: 02/04/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yamatake, Mineo
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): DUDEK, JAMES A
• Application Number:
  US08/013,508
• Time in Patent Office: 712 Days
• Field of Search: 330/103, 330/260, 330/293, 330/292, 330/302, 330/253, 330/107, 330/110, 330/69, 307/475, 307/296.8, 307/490, 307/494
• US Class Current: 330/260
• CPC Class Codes: H03H 11/48 simulating reactances
• CPC Class Codes: H03H 11/483 Simulating capacitance multipliers

Abstract

A monolithic switching regulator on chip loop frequency compensation circuit is described. An op-amp is provided with a conventional small frequency compensation capacitor, which determines its unity gain frequency and an input resistor. The op-amp incorporates 100% negative feedback. When driven at a frequency that is below its unity gain frequency the noninverting input of the op-amp displays a capacitance having a value on the order of nanofarads, which value would ordinarily require an excessive chip area if fabricated as an actual capacitor. This capacitance value is useful in the on chip loop frequency compensation of a switching regulator where the switching frequency is operated at about 150 kHZ.

Claims

1. A capacitance multiplying circuit for use on an integrated circuit chip for providing a relatively large on chip capacitance useful in loop frequency compensation functions, said circuit comprising:

an op-amp having inverting and noninverting inputs, a single ended output and a unity gain frequency;

a first resistor connected between said inverting and noninverting inputs;

means for coupling said op-amp output to its inverting input; and

means for driving said op-amp noninverting input at a frequency that is below the op-amp unity gain frequency whereby a relatively large equivalent shunt capacitance is present at said noninverting input.

2. The capacitance multiplying circuit of claim 1 wherein said op-amp further includes a small internal frequency compensation capacitor which determines said op-amp unity gain frequency.

3. The capacitance multiplier of claim 2 wherein said equivalent shunt capacitance is proportional to the reciprocal of said first resistor value multiplied by said unity gain frequency.

4. The capacitance multiplier circuit of claim 2 wherein a second resistor couples said op-amp noninverting input to complete said on chip loop frequency compensation function.

5. A method for providing a large effective capacitance at a non-inverting terminal of an op-amp, said op-amp having a resistance coupled between an inverting terminal of said op-amp and said non-inverting terminal, said method comprising the steps of:

applying an input signal to said non-inverting terminal;

generating an output signal at an output terminal of said op-amp in response to said input signal;

providing said output signal to said inverting terminal; and

generating a signal across said resistance in response to said output signal at said input terminal, wherein said signal across said resistance causes an effective shunt capacitance to appear at said non-inverting terminal.

6. The method of claim 5 wherein said equivalent shunt capacitance is inversely proportional to the product of said resistance and a unity gain frequency of said op-amp.