Automatic selection of an operating frequency in a low-gain broadband phase lock loop system

• US 5,382,921 A
• Filed: 11/23/1992
• Issued: 01/17/1995
• Est. Priority Date: 11/23/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mentzer, Ray A., Estrada, Julio R.
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US07/984,172
• Time in Patent Office: 785 Days
• Field of Search: 331/1 A, 331/17, 331/25, 331/34, 331/57, 331/108 B, 331/108 C, 331/179, 331/10, 328/155
• US Class Current: 331/1.00A
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Claims

1. A phase-lock loop system for automatically frequency-locking a signal in phase with a reference signal, said system comprising:

a. a reference source for providing a reference signal;

b. a phase and frequency detector for comparing said reference signal to said signal, said phase and frequency detector coupled to said reference source;

c. an up/down counter coupled to said phase and frequency detector;

d. a digital-to-analog converter for providing an analog control signal, said digital-to-analog converter coupled to said up/down counter;

e. a decoder for providing a digital control signal, said decoder coupled to said up/down counter; and

f. a ring oscillator having a plurality of stages connected in tandem, said ring oscillator coupled to said digital-to-analog converter and to said decoder, said ring oscillator having a digital input for receiving said digital control signal and an analog input for receiving said analog control signal, wherein each of said plurality of stages of said ring oscillator includes an anti-high gain circuit.

2. Phase-lock loop system of claim 1 further comprising a down counter coupled to said ring oscillator.

3. Phase-lock loop system of claim 1 wherein said up/down counter provides a first digital signal to said decoder and a second digital signal to said digital-to-analog converter.

4. Phase-lock loop system of claim 1 wherein said up/down counter is an eleven-bit up/down counter.

5. Phase-lock loop system of claim 1 wherein said decoder is a one-of-eight decoder.

6. Phase-lock loop system of claim 2 wherein said down counter is a three-bit down counter.

7. Phase-lock loop system of claim 2 further comprising a master reset connected to said up/down counter and to said down counter.

8. Phase-lock loop system of claim 1 further comprising a sense amplifier coupled between said digital-to-analog converter and said ring oscillator.

9. Phase lock loop system of claim 1 with each of said plurality of stages of said ring oscillator providing a frequency response and comprising:

i. a digital input terminal, and

ii. an inverter having an input and an output and a feedback connection from said output to said input, with said inverter coupled to said anti-high-gain circuit,

wherein, when one of said plurality of stages is actuated in response to said digital control signal at said digital input terminal, said frequency response of the actuated stage is adjusted in response to said analog control signal.

10. Phase-lock loop system of claim 9 further comprising a three-state select circuit for controlling feedback at said inverter, said three-state select circuit coupled to said inverter and coupled to said digital input terminal.

11. A method of automatically frequency-locking a signal in phase with a reference signal, said method comprising the steps of:

a. comparing a reference signal with said signal;

b. generating up and down commands;

c. providing, in response to said up and down commands, a first digital control signal and a second digital control signal;

d. converting said first digital control signal to an analog signal;

e. decoding said second digital control signal to a decoded digital control signal;

f. actuating a single stage in a multi-stage ring oscillator by applying said decoded digital control signal to a digital input of said multi-stage ring oscillator;

g. providing to each stage of said multi-stage ring oscillator means for regulating high gain of said stage; and

h. fine controlling said multi-stage ring oscillator by applying said analog signal to an analog input of said multi-stage ring oscillator.

12. Method of claim 11 further comprising the step of generating a lock signal for indicating that said signal is frequency-locked with said reference signal.

13. Method of claim 11 wherein said analog signal is a control current further comprising the step of converting said control current to a control voltage.