Integrated circuit for physiological signal measurement

• US 5,382,956 A
• Filed: 04/30/1992
• Issued: 01/17/1995
• Est. Priority Date: 04/30/1992
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baumgartner, Richard A., Herleikson, Earl C., Moore, Charles E.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/876,645
• Time in Patent Office: 992 Days
• Field of Search: 341/155, 341/126, 341/159, 341/899
• US Class Current: 341/155
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: G16H 40/40 for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
• CPC Class Codes: G16H 40/63 for local operation
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45775 by using cross switches
• CPC Class Codes: H03F 3/45968 by offset reduction

Abstract

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Claims

1. An integrated circuit comprising:

a plurality of analog signal amplifiers, each said analog signal amplifier having an amplifier input connected to an external input voltage and a signal amplifier output; and

wherein each said signal amplifier output is resistively connected to an input of an analog to digital converter means for receiving said signal amplifier output and for converting said signal amplifier output to a digital output; and

an averaging amplifier means for receiving a plurality of analog averaging inputs, for generating a sum of said plurality of analog averaging inputs, and for generating an external analog averaging output by amplifying said sum; and

wherein there is a one-to-one correspondence between said analog averaging inputs and said signal amplifier outputs; and

wherein each analog averaging input is switchably connected to one corresponding signal amplifier output; and

averaging switching means for receiving digital averaging selection bits and for selecting which of said analog averaging inputs is switched to a corresponding signal amplifier output, in response to said digital averaging selection bits; and

digital control means for generating said averaging selection bits in response to an external digital command input.

2. An integrated circuit as in claim 1 wherein each analog signal amplifier in said plurality of analog signal amplifiers further comprises:

gain switching means for receiving digital gain selection bits and for selecting a gain of said analog signal amplifier in response to said digital gain selection bits; and

wherein said digital control means further comprises means for generating said digital gain selection bits in response to said external digital command input.

3. An integrated circuit as in claim 1 wherein each said analog to digital converter means further comprises:

offset means for receiving said digital output and for detecting when said digital output is outside an operating range and for generating an offset voltage if said digital output is outside said operating range and for subtracting said offset voltage at said input of said analog to digital converter means, thereby bringing said digital output back within said operating range.

4. An integrated circuit as in claim 1 wherein each analog signal amplifier in said plurality of signal amplifiers is a chopper stabilized amplifier with chopper stabilized common mode feedback.

5. An integrated circuit as in claim 4 wherein each analog signal amplifier in said plurality of analog signal amplifiers further comprises;

gain switching means for receiving digital gain selection bits and for selecting a gain of said analog signal amplifier in response to said digital gain selection bits; and

wherein said digital control means further comprises means for generating said digital gain selection bits in response to said external digital command input.

6. An integrated circuit as in claim 5 wherein each said analog to digital converter means further comprises:

offset means for receiving said digital output and for detecting when said digital output is outside an operating range and for generating an offset voltage if said digital output is outside said operating range and for subtracting said offset voltage at said input of said analog to digital converter means, thereby bringing said digital output back within said operating range.

7. An integrated circuit comprising:

a plurality of analog signal amplifiers, each said analog signal amplifier having an amplifier input connected to an external input voltage and a signal amplifier output; and

wherein each said signal amplifier output is switchably and resistively connected to an input of an analog to digital converter means for receiving said signal amplifier output and for converting said signal amplifier output to a digital output; and

an averaging amplifier means for receiving a plurality of analog averaging inputs, for generating a sum of said plurality of analog averaging inputs, and for generating an external analog averaging output by amplifying said sum; and

wherein there is a one-to-one correspondence between said analog averaging inputs and said signal amplifier outputs; and

wherein each analog averaging input is switchably connected to one corresponding signal amplifier output; and

a plurality of impedance measurement means for generating a digital impedance signal, each said impedance measurement means comprising;

impedance signal generating means for generating an alternating output current through an external impedance, thereby generating an alternating voltage across said external impedance; and

rectification means for receiving and rectifying said alternating voltage, thereby generating a DC analog impedance voltage; and

analog to digital conversion means for receiving said DC analog impedance voltage and for converting said DC analog impedance voltage to said digital impedance signal.

8. An integrated circuit as in claim 7 wherein each said impedance signal generating means further comprises;

first and second current source means for sourcing current to said external impedance through a chopper circuit; and

third and fourth current source means for receiving and sinking chopped current returning from said external impedance; and

wherein said first and second current source means are controlled by a first chopper stabilized current source amplifier; and

wherein said third and fourth current source means are controlled by a second chopper stabilized current source amplifier.

9. An integrated circuit as in claim 7 wherein each said analog to digital converter means further comprises:

offset means for receiving said digital output and for detecting when said digital output is outside an operating range and for generating an offset voltage if said digital output is outside said operating range and for subtracting said offset voltage at said input of said analog to digital converter means, thereby bringing said digital output back within said operating range.

10. An integrated circuit as in claim 7 wherein each analog signal amplifier in said plurality of analog signal amplifiers is a chopper stabilized amplifier with chopper stabilized common mode feedback.

11. An integrated circuit as in claim 10 wherein each said impedance signal generating means further comprises:

first and second current source means for sourcing current to said external impedance through a chopper circuit; and

third and fourth current source means for receiving and sinking chopped current returning from said external impedance; and

wherein said first and second current source means are controlled by a first chopper stabilized current source amplifier; and

wherein said third and fourth current source means are controlled by a second chopper stabilized current source amplifier.

12. An integrated circuit as in claim 11 wherein each said analog to digital converter means further comprises:

offset means for receiving said digital output and for detecting when said digital output is outside an operating range and for generating an offset voltage if said digital output is outside said operating range and for subtracting said offset voltage at said input of said analog to digital converter means, thereby bringing said digital output back within said operating range.

13. An integrated circuit comprising:

a plurality of analog signal amplifiers, each said analog signal amplifier having an amplifier input connected to an external input voltage and a signal amplifier output; and

a first plurality of analog to digital converter means for receiving and converting an analog A/D input to a digital output signal, wherein there is a one-to-one correspondence between said first plurality of analog to digital converter means and said plurality of analog signal amplifiers; and

a second plurality of analog to digital converter means, comprising a subset of said first plurality of analog to digital converter means, wherein analog to digital converter means in said second plurality of analog to digital converter means have switchable inputs; and

a plurality of impedance measurement means for generating a digital impedance signal, each said impedance measurement means comprising;

impedance signal generating means for generating an alternating output current through an external impedance, thereby generating an alternating voltage across said external impedance; and

rectification means for rectifying said alternating voltage, thereby generating a DC impedance voltage; and

wherein there is a one-to-one correspondence between said second plurality of analog to digital conversion means and said plurality of impedance measurement means; and

wherein, for analog to digital converter means which are in said first plurality of analog to digital converter means but which are not in said second plurality of analog to digital converter means, each analog A/D input is resistively connected to a corresponding signal amplifier output; and

wherein analog to digital converter means in said second plurality of analog to digital converter means further comprise;

A/D input switching means for receiving digital A/D switch selection bits and for selecting whether said analog A/D input is resistively connected to a corresponding signal amplifier output or is connected to a corresponding DC impedance voltage, in response to said digital A/D switch selection bits; and

digital control means for receiving an external digital command input and for generating said A/D switch selection bits in response to said external digital command input.

14. An integrated circuit as in claim 13 wherein each said analog signal amplifier further comprises:

gain switching means for receiving digital gain selection bits and for selecting a gain of said analog signal amplifier in response to said digital gain selection bits; and

wherein said digital control means further comprises means for generating said digital gain selection bits in response to said external digital command input.

15. An integrated circuit as in claim 14 further comprising;

an averaging amplifier means for receiving a plurality of analog averaging inputs, for generating a sum of said plurality of analog averaging inputs, and for generating an external analog averaging output by amplifying said sum; and

wherein there is a one-to-one correspondence between said analog averaging inputs and said signal amplifier outputs; and

wherein each analog averaging input is switchably connected to one corresponding signal amplifier output.

16. An integrated circuit as in claim 15 further comprising:

averaging switching means for receiving digital averaging selection bits and for selecting which of said analog averaging inputs is switched to a corresponding signal amplifier output, in response to said digital averaging selection bits; and

wherein said digital control means further comprises means for generating said averaging selection bits in response to said external digital command input.

17. An integrated circuit as in claim 16 wherein each analog signal amplifier in said plurality of analog signal amplifiers is a chopper stabilized amplifier with chopper stabilized common mode feedback.

18. An integrated circuit as in claim 17 wherein each analog to digital converter means in said first plurality of analog to digital converter means further comprises:

offset means for receiving said digital output and for detecting when said digital output is outside an operating range and for generating an offset voltage if said digital output is outside said operating range and for subtracting said offset voltage at said input of said analog to digital converter means, thereby bringing said digital output back within said operating range.

19. An integrated circuit as in claim 18 wherein each said impedance signal generating means further comprises;

first and second current source means for sourcing current to said external impedance through a chopper circuit; and

third and fourth current source means for receiving and sinking chopped current returning from said external impedance; and

wherein said first and second current source means are controlled by a first chopper stabilized current source amplifier; and

wherein said third and fourth current source means are controlled by a second chopper stabilized current source amplifier.