Design verification device

• US 5,383,132 A
• Filed: 06/05/1992
• Issued: 01/17/1995
• Est. Priority Date: 10/30/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Matsumoto, Hisashi, Shinohara, Hirofumi, Tsujihashi, Yoshiki
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MCFADDEN, SUSAN IRIS
• Application Number:
  US07/894,663
• Time in Patent Office: 956 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A design verification device includes a diagram data memory for storing designed diagram data, a design reference value memory for storing a design reference value, a determination circuit for making determination with different weight between intersecting directions of a diagram to either the distance or the design reference value in calculating the distance between diagram data provided from the diagram data memory means for making determination whether the calculated distance follows the design reference value; and an error signal output circuit for providing an error signal when determination is made that the design reference value is not followed by the determination circuit.

Claims

1. A design verification device for making determination whether the design is carried out according to a previously set design reference value by calculating the distance of a straight line between boundaries of design diagram data in a physical space, said design verification device comprising:

diagram data memory means for storing design diagram data,

design reference value memory means for storing design reference values,

determination means for making determination whether said distance conforms to the corresponding design reference value with different weight given to different intersecting directions in calculating the distance of the straight line between boundaries of design diagram data, and

error signal output means for providing an error signal when determination is made by said determination means that the distance does not conform to the corresponding design reference value.

2. The design verification device according to claim 1, wherein said diagram data comprises two dimensional diagram data.

3. The design verification device according to claim 2, wherein either of said distance or said design reference value of the corner portion where the sides of a diagram intersect is processed as an elliptical arc.

4. The design verification device according to claim 2, wherein said diagram data comprises diagram data in a plan design drawing of a semiconductor integrated circuit.

5. The design verification device according to claim 1, wherein said diagram data comprises three dimensional diagram data.

6. The design verification device according to claim 5, wherein either said distance or said design reference value in the corner portion where the faces of a diagram intersect is processed as an elliptical curved surface.

7. The design verification device according to claim 1, wherein said different intersecting directions are orthogonal to each other.

8. A design verification device for making determination whether the design is carried out according to a previously set design reference value by calculating the distance of a straight line between boundaries of design diagram data in a physical space, said design verification device comprising:

diagram data memory means for storing design diagram data, an error determination boundary surrounding a design diagram data,

design reference value memory means for storing design reference values,

determination means for making determination whether said distance conforms to the corresponding design reference value indicating that the design diagram data does not transgress the error determination boundary, and

error signal output means for providing an error signal when determination is made by said determination means that the design reference value is not followed, wherein

said error determination boundary comprises

i. a continuous closed curved line consisting of a straight line and elliptical arc for two dimensional design diagram data, and

ii. a continuous closed curved surface consisting of a plane and elliptic surface for three dimensional design diagram data.