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Fast circuit and method for detecting predetermined bit patterns

  • US 5,383,142 A
  • Filed: 10/01/1993
  • Issued: 01/17/1995
  • Est. Priority Date: 10/01/1993
  • Status: Expired due to Term
First Claim
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1. A processor for detecting a specified bit pattern in the contents of one or more registers, each register having a plurality of bits, said processor comprising a hierarchical array comprising a plurality of ordered levels of processors labeled 1, 2, . . . M, each level of processors having one or more processing modules, each processing module receiving a plurality of state inputs and generating therefrom a state output, said processing modules in level 1 of said processors having said state inputs connected to selected bits in said registers and said processing modules in the kth level of said hierarchy having said state inputs connected to state outputs of processing modules in level (k-1) of said hierarchy for k=2 to M, wherein each of said processing modules in said levels labeled with 2, 3, . . . , M further comprise means for receiving a plurality of input values and means for generating an output value based on said state inputs and said input values, said receiving means of said processing modules in the kth level of said hierarchy having said receiving means connected to said output generating means of processing modules in level (k-1) of said hierarchy for k=2 to M, said output value providing information on the potential location of said specified bit pattern, and wherein each said processing module in said level labeled 1 includes means for generating an output signal based on said selected bits connected thereto.

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