Resequencing device for a node of a cell switching system

• US 5,383,182 A
• Filed: 11/12/1993
• Issued: 01/17/1995
• Est. Priority Date: 11/30/1992
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Guebels, Pierre-Paul F. M. M., Therasse, Yves
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): VU, HUY DUY
• Application Number:
  US08/152,594
• Time in Patent Office: 431 Days
• Field of Search: 370/60, 370/60.1, 370/94.1, 370/58.1, 370/58.2, 370/58.3, 370/91, 370/92, 370/93, 370/94.2, 370/99, 370/110.1, 370/825.52, 370/825.51, 370/825.5
• US Class Current: 370/394
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/565 Sequence integrity
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics

Abstract

The device is for telecommunication networks with an asynchronous transfer mode and contains, in particular:

a time stamp generator (TSG), for assigning a time stamp to each cell;

a buffer memory (BM);

an address memory (FSAM) to memorize the address of the first sub-cell of each cell;

a linking memory (LM);

a circuit (CU) for finding the buffer memory address containing the first sub-cell of a cell; this circuit comprises, in particular: a memory that is accessible by its content, for memorizing the waiting cell identifiers, each containing the identity of a time period during which the waiting delay of the cell expires, and of the identity of at least one output from which the cell is to be emitted; and a queuing memory for each output, where the order number is recorded each time the waiting delay of at least one cell, which must be emitted from that output, expires; each queuing memory is of the type accessible by its content, and the numbers are searched in ascending order when this output becomes available.

Claims

1. Resequencing device (RU) for a node of a system for switching cells, each cell comprising a variable number of sub-cells of fixed length, said node comprising a switching network (SW) through which said cells are transmitted with first variable delays, all the sub-cells of a same cell being subjected to a same first delay;

said resequencing device (RU) including means for storing all said cells that have been transmitted through said switching network and for then sending them to at least one output of said resequencing device after respective waiting delays constituting respective second delays having expired so that for each cell a sum of said first delay and said respective second delay is equal to a predetermined value substantially equal for all said cells;

said means including;

a buffer memory (BM) responsive to a cell having been transmitted through said switching network, for storing all the sub-cells of said cell transmitted through said switching network and received by said resequencing device;

an address memory (FSAM) responsive to said storage of said cell in said buffer memory (BM), for storing an address (FSA) of a location of said buffer memory containing a first sub-cell of said cell;

means (TSG, IC1, . . . , ICN, CU) responsive to said storage of said cell in said buffer memory (BM), for finding in said address memory a location containing an address (FSA'"'"') of said location of said buffer memory (BM) containing said first sub-cell of said cell when said waiting delay of said cell has expired and when an output on which said cell has to be sent is available;

wherein said means for finding said address (FSA'"'"') of said location of said buffer memory containing said first sub-cell of said cell includes;

a waiting-cell memory (VIM), addressable by its content, for storing a waiting-cell identifier (TSTP-OA) when said cell is stored in said buffer memory (BM);

said waiting-cell identifier (TSTP-OA) being stored at a location of said waiting-cell memory (VIM) with an address (FA) identical to an address of said location of said address memory (FSAM) where said address (FSA) of said location of said first sub-cell in said buffer memory (BM) is stored; and

said waiting-cell identifier including;

a time label (TSTP) identifying a time slot period within which said waiting delay of said cell stored in said buffer memory (BM) will expire and an identity (OA;

OM) of at least one output of said resequencing device to which said cell has to be sent;

means (TC, AC) responsive to said waiting-cell identifier, for finding in said waiting-cell memory (VIM) said waiting-cell identifier (TSTP-OA) of each cell when its waiting delay expires, and for providing for each thus found waiting-cell identifier said identity of said at least one output included in said waiting-cell identifier and an address (NA) of a location of said waiting-cell memory (VIM) containing said found waiting-cell identifier;

queuing memories (QC1, . . . , QCN) respectively associated with the outputs of said resequencing device and addressable by their content, for storing in response to said output identity included in said waiting-cell identifier and to said address (NA) of said location of said waiting-cell memory (VIM) containing said found waiting-cell identifier, in a selected said queuing memory associated to an output having said output identity, a sequence number for each cell which has to be sent to said output having said output identity;

means (DMX, SNL1, . . . , SNLN) responsive to said address of said location of said waiting-cell memory (VIM), for determining and writing said sequence number in said selected queuing memory at said address (NA) provided by said means (TC, AC) for finding said waiting-cell identifier of each cell when its waiting delay expires;

means (SNL1, . . . , SNLN, FFO1, . . . , FFON) responsive to an output availability signal (IDL) provided by said outputs of said resequencing device and indicating whether a respective one of said outputs is available or not, for finding, in ascending order, each sequence number (SN'"'"') stored in said queuing memory when said output associated thereto becomes available; and

for returning an address (NA'"'"') of a location of said queuing memory containing a found sequence number (SN'"'"');

means (MUX) responsive to said address returned by said means for finding each sequence number, for reading an address (FSA'"'"') of a location of a first sub-cell in said address memory (FSAM) at said address returned by said means (SNL1, . . . , SNLN, LRSN) for finding each number.

2. Resequencing device according to claim 1, wherein said means (TC, AC) for finding in said waiting-cell memory (VIM) said waiting-cell identifier of each cell when its waiting delay expires and for providing for each found waiting-cell identifier said output identity included in said waiting-cell identifier and said address (NA) of said waiting-cell memory (VIM) that contains said found identifier, comprise:

means (TC) for providing to a comparison input of said waiting-cell memory (VIM), at each time slot period corresponding to an expiring waiting delay, a sequence of cell-to-send identifiers (TSTP'"'"'-OA'"'"') each constituted by an identity (TSTP'"'"') of the current time slot period and by an identity (OA'"'"') of a single output of said resequencing device;

said sequence including the identities (OA'"'"') of all the outputs of said resequencing device; and

means (AC) responsive to said waiting-cell identifier, coupled to outputs of said waiting-cell memory (VIM) for successively providing each address (NA) of said waiting-cell memory containing a said found waiting-cell identifier.

3. (Amended) Resequencing device according to claim 1, wherein said means (DMX, SNL1, . . . , SNLN) for determining and writing said sequence number (SN) in said selected queuing memory (QC1, . . . , QCN) comprise, for each output of said resequencing device, a counter (LWSN) providing said sequence number (SN) which is incremented by one unit when at least one waiting-cell identifier is found in said waiting-cell memory (VIM) for a given time slot period and a given output of said resequencing device.

4. Resequencing device according to claim 1, wherein said means for finding each sequence number (SN'"'"') includes, for each output of said resequencing device, a counter (LRSN) providing said sequence number to be found (SN'"'"') which is incremented by one unit when said output of said resequencing device becomes available, said sequence number to be found (SN'"'"') being applied to a comparison input of said queuing memory (QC1, . . . , QCN) associated with said output of said resequencing device.