Semiconductor memory device having an error correction circuit and an error correction method of data in a semiconductor memory device
First Claim
1. A semiconductor device comprising:
- a memory cell array having a plurality of data and a plurality of parity data stored therein,means for reading out said plurality of data and said plurality of parity data from said memory cell array anderror correction means for correcting an error in said plurality of data by applying operation according to a predetermined Hamming matrix to said plurality of data and said plurality of parity data read out by said reading means,wherein said plurality of data are equally divided into a first group and a second group,wherein said error correction means comprisessyndrome signal producing means for producing a plurality of syndrome signals on the basis of said first and second groups of data and said plurality of parity data read out from said memory cell array by said reading means,group selecting means for sequentially selecting the data of said first group and said second group read out from said memory cell array by said reading means,correction signal producing means for sequentially producing a correction signal for said first group of data and a correction signal for said second group of data in synchronization with the selecting operation of said group selecting means, in response to said syndrome signals produced by said syndrome signal producing means, anddata correction means for correcting an error in the group of data selected by said group selecting means according to a correction signal produced by said correction signal producing means.
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Accused Products
Abstract
A mask ROM having an ECC for error correction by carrying out operation according to a Hamming matrix in which all but 2 of 6 elements in one column and the other column match each other. The columns correspond to 32 data that will be provided to an external source, and the one column corresponds to the other column by 16 columns. The ECC is implemented so that one half of 32 correction signals with which exclusive ORs are to be taken with 32 data, are generated by a circuit identical to that of a circuit for generating the other half of the 32 correction signals; and the circuit for taking the exclusive ORs from one half of the 32 data and the corresponding correction signals can be used for taking exclusive ORs from the remaining half of the 32 data and the corresponding correction signals. The number of component elements for the correction signal generator and for the data correction circuit, and the number of input signal lines to the data correction circuit are reduced to a half, alleviating the circuit complexity of the entire ECC in comparison with that of a conventional one.
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Citations
17 Claims
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1. A semiconductor device comprising:
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a memory cell array having a plurality of data and a plurality of parity data stored therein, means for reading out said plurality of data and said plurality of parity data from said memory cell array and error correction means for correcting an error in said plurality of data by applying operation according to a predetermined Hamming matrix to said plurality of data and said plurality of parity data read out by said reading means, wherein said plurality of data are equally divided into a first group and a second group, wherein said error correction means comprises syndrome signal producing means for producing a plurality of syndrome signals on the basis of said first and second groups of data and said plurality of parity data read out from said memory cell array by said reading means, group selecting means for sequentially selecting the data of said first group and said second group read out from said memory cell array by said reading means, correction signal producing means for sequentially producing a correction signal for said first group of data and a correction signal for said second group of data in synchronization with the selecting operation of said group selecting means, in response to said syndrome signals produced by said syndrome signal producing means, and data correction means for correcting an error in the group of data selected by said group selecting means according to a correction signal produced by said correction signal producing means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of correcting, according to a predetermined Hamming matrix, an error of data in a semiconductor memory device having a memory cell array in which a plurality of data and a plurality of parity data corresponding to said plurality of data are stored therein, wherein said plurality of data is equally divided into a first group and a second group, said method comprising the steps of:
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reading out said first and second groups of data and said plurality of parity data from said memory cell array, producing a plurality of syndrome signals on the basis of said read out first and second groups of data and said plurality of parity data, sequentially selecting said read out first and second groups of data, producing sequentially a correction signal for said first group of data and a correction signal for said second group of data in synchronization with said selection in response to said produced syndrome signals, and correcting an error in said selected group of data in response to said produced correction signal. - View Dependent Claims (17)
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Specification