Method for reduction of off-current in thin film transistors

• US 5,384,271 A
• Filed: 10/04/1993
• Issued: 01/24/1995
• Est. Priority Date: 10/04/1993
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Possin, George E., Kwasnick, Robert F.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/130,807
• Time in Patent Office: 477 Days
• Field of Search: 437/41, 437/101, 437/909, 437/21, 437/228, 437/40, 156/651
• US Class Current: 438/158
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: Y10S 438/958 Passivation layer

Abstract

A method of fabricating a thin film transistor having reduced off-current leakage includes the steps of forming a TFT body with a channel region disposed between a source electrode and a drain electrode and then passivating the exposed portion of the channel region. The passivation includes the steps of wet etching the exposed portions of the channel region in an hydrofluoric acid etchant for a first selected etch time; dry etching the exposed channel region in a reactive ion etching procedure for a second selected etch time; wet etching the channel region again with hydrofluoric acid for a third selected etch time; and then treating the channel region with a cleansing agent, such as photoresist stripper; and annealing the exposed portion of the channel region.

Claims

1. A method of fabricating a thin film transistor (TFT) having relatively low off-current comprising the steps of:

forming a TFT body having a gate electrode, a gate dielectric layer disposed over said gate electrode, a semiconductor layer disposed over said gate dielectric layer, a doped semiconductor layer disposed over said semiconductor layer, and a source-drain metal layer disposed over said doped semiconductor layer;

forming a channel region in said TFT body, said channel region being exposed and defined by etching said source-drain metal layer, the underlying doped semiconductor layer, and a portion of the underlying semiconductor layer so as to form source and drain electrodes; and

passivating the channel region, the step of passivating further comprising the steps of wet etching the exposed channel region for a first etch time, dry etching the exposed channel region for a second etch time, wet etching the exposed channel region for a third etch time, treating the exposed channel region with a cleansing solution, and annealing the exposed channel region.

2. The method of claim 1 wherein the steps of wet etching said exposed channel region for a first etch time and for a third etch time further comprises applying an etchant comprising hydrofluoric acid (HF).

3. The method of claim 2 wherein the step of dry etching said exposed channel region comprises reactive ion etching (RIE) said exposed channel region.

4. The method of claim 3 wherein said cleansing solution comprises photoresist stripper.

5. The method of claim 3 wherein said cleansing solution comprises distilled water.

6. The method of claim 3 wherein the step of annealing said exposed channel region comprises baking said TFT body at a temperature of about 250°

C. for a period of about 30 minutes.

7. The method of claim 3 wherein said first etch time is in the range between about 20 seconds to 90 seconds.

8. The method of claim 3 wherein said second etch time is in the range between about 15 seconds to 60 seconds.

9. The method of claim 3 wherein said third etch time is in the range between about 30 seconds to 90 seconds.

10. The method of claim 4 wherein the step of treating the exposed channel region with photoresist stripper comprises applying said photoresist stripper to said exposed channel region for a period of about 5 minutes and a temperature of about 80°

C.

11. The method of claim 1 wherein said doped semiconductor material comprises heavily doped n+silicon.

12. The method of claim 1 wherein said semiconductor material comprises amorphous silicon.

13. The method of claim 3 further comprising the step of depositing a layer of dielectric passivation material over said TFT body and said channel region.