Current limiting circuit and method of manufacturing same

• US 5,384,529 A
• Filed: 01/28/1994
• Issued: 01/24/1995
• Est. Priority Date: 02/01/1993
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nakago, Manabu
• Primary Examiner(s): Peckman, Kristine L.
• Assistant Examiner(s): To, E.
• Application Number:
  US08/188,319
• Time in Patent Office: 361 Days
• Field of Search: 323/312, 323/907, 323/299, 323/234, 323/282
• US Class Current: 323/312
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

A current limiting circuit which includes a vertical MOS transistor as an output transistor has a clamping voltage that can be established with high accuracy, and once established, is less dependent on temperature. The gate of an output N-channel VDMOS transistor is connected to a constant-voltage circuit composed of an N-channel VDMOS transistor having the same characteristics as those of the output N-channel VDMOS transistor and two series-connected resistors which supply a divided voltage to the gate of the N-channel VDMOS transistor. The clamping voltage between the gate and source of the output N-channel VDMOS transistor can be adjusted based on the voltage divided by the resistors of the constant-voltage circuit. The temperature characteristics of the output N-channel VDMOS transistor and the constant-voltage circuit are held in phase with each other to reduce variations in the clamping voltage caused by temperature variations.

Claims

1. A current limiting circuit comprising:

an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential through a load, and a source connected to ground;

an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a source connected to ground;

first and second resistors connected in series between the gate of said first N-channel vertical MOS transistor and a drain of said N-channel MOS transistor; and

a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the gate of said first N-channel vertical MOS transistor, a source connected to the drain of said N-channel MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.

2. A current limiting circuit comprising:

an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential, and a source connected to a load;

an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a drain connected to the gate of said first N-channel vertical MOS transistor;

first and second resistors connected in series between a source of said N-channel MOS transistor and said load; and

a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the source of said N-channel MOS transistor, a source connected to the source of said first N-channel vertical MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.