Constant transconductance bias circuit and method

• US 5,384,548 A
• Filed: 08/25/1993
• Issued: 01/24/1995
• Est. Priority Date: 08/25/1993
• Status: Expired due to Term

• Current Assignee: Ohio State University
• Original Assignee: Ohio State University
• Inventors: Sakurai, Satoshi, Ismail, Mohammed
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/111,708
• Time in Patent Office: 517 Days
• Field of Search: 330/253, 330/254, 330/257, 330/258, 330/261
• US Class Current: 330/253
• CPC Class Codes: H03F 2200/162 FETs are biased in the weak inversion region
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

The reduction of the power supply voltage of VLSI circuits to 3.3 volts results in a significant loss in input and output swing in traditional CMOS analog circuits. In order to achieve rail-to-rail operation, n-channel and p-channel MOSFETs are placed in parallel so that at least one type of transistors are operating in a high gain region throughout the entire input range. However, circuit characteristics change as transistors turn on and off. A constant transconductance bias means enables the rail-to-rail CMOS differential stage to possess a constant transconductance over the entire common mode voltage range. Significantly, the bias circuit does not require any matching between the transistors of opposite types.

Claims

1. An integrated circuit comprising:

a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough; and

constant transconductance bias means, electrically connected to said differential stage, for monitoring one of the first and second bias currents and dynamically controlling the other of the first and second bias currents to maintain constant transconductance of said differential stage.

2. An integrated circuit according to claim 1 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of p-type conductivity.

3. An integrated circuit according to claim 2 wherein the dynamically controlled one of said first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of n-type conductivity.

4. An integrated circuit according to claim 1 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of n-type conductivity.

5. An integrated circuit according to claim 4 wherein the dynamically controlled one of the first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of p-type conductivity.

6. An integrated circuit according to claim 1 further comprising a first current source, electrically coupled to the constant transconductance bias means, for limiting said dynamically controlled bias current when the FETs through which the monitored bias current flows are operating in weak inversion.

7. An integrated circuit according to claim 6 further comprising a second current source, electrically coupled to the constant transconductance bias means, for limiting said monitored bias current when the FETs through which the dynamically controlled bias current flows are operating in weak inversion.

8. An integrated circuit according to claim 7 wherein the constant transconductance bias means maintains the current ratio of the first current source to the second current source equal to a predetermined constant value.

9. An integrated circuit according to claim 8 wherein said predetermined constant value is equal to the ratio of device transconductance parameter of the FETs through which the monitored bias current flows and device transconductance parameter of the FETs through which the dynamically controlled bias current flows.

10. An integrated circuit according to claim 1 further comprising a constant voltage source, electrically coupled to the constant transconductance bias means, for providing a bias voltage thereto.

11. An integrated circuit according to claim 1 further comprising a constant current source, electrically coupled to the constant transconductance bias means, for providing a bias current thereto.

12. An integrated circuit comprising:

differential input means including a plurality of transistors of a first conductivity type having a first device transconductance parameter and a plurality of transistors of a second conductivity type having a second device transconductance parameter which is different from said first device transconductance parameter, said first and second plurality of transistors defining a first input and a second input for receiving a first and a second input signal and at least one output for providing an output signal which is proportional to the difference between the first and second input signals; and

constant transconductance bias means, electrically connected to said differential input means, for dynamically controlling the differential input means to maintain constant transconductance of the differential input means, notwithstanding the different device transconductance parameters of said first and second conductivity transistors.

13. An integrated circuit according to claim 12 further comprising:

a first bias current source and a second bias current source, electrically connected to said differential input means and said constant transconductance bias means, wherein said constant transconductance bias means monitors one of the first and second bias current sources and dynamically controls the other of the first and second bias current sources.

14. A method for operating an integrated circuit, the integrated circuit comprising a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough, said method comprising the steps of:

monitoring one of the first and second bias currents; and

dynamically controlling the other of the first and second bias currents to maintain constant transconductance of the differential stage.

15. A method according claim 14 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of p-type conductivity.

16. A method according to claim 15 wherein the dynamically controlled other of said first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of n-type conductivity.

17. A method according to claim 14 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of n-type conductivity.

18. A method according to claim 17 wherein the dynamically controlled other of the first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of p-type conductivity.

19. A method according to claim 14 further comprising the step of:

limiting said dynamically controlled bias current to a predetermined maximum value when the FETs through which the monitored bias current flows are operating in weak inversion.

20. A method according to claim 19 further comprising the step of:

limiting said monitored bias current to a second predetermined maximum value when the FETs through which the dynamically controlled bias current flows are operating in weak inversion.

21. A method according to claim 20 wherein said dynamically controlling step comprises the step of maintaining a ratio of the first predetermined maximum value to the second predetermined maximum value equal to a predetermined constant value.

22. A method according to claim 21 wherein said predetermined constant value is equal to the ratio of device transconductance parameter of the FETs through which the monitored bias current flows and device transconductance parameter of the FETs through which the dynamically controlled bias current flows.