Battery saving arrangement for selectively addressable, portable receivers

• US 5,384,564 A
• Filed: 01/23/1992
• Issued: 01/24/1995
• Est. Priority Date: 01/23/1992
• Status: Expired due to Fees

• Current Assignee: Keith H. Wycoff
• Original Assignee: Keith H. Wycoff
• Inventors: Dittmer, William H., Wycoff, Keith H.
• Primary Examiner(s): Horabik, Michael
• Application Number:
  US07/824,592
• Time in Patent Office: 1,097 Days
• Field of Search: 340/825.44, 340/825.48, 340/311.1, 455/38.3, 455/343, 455/228
• US Class Current: 340/7.35
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 88/022 Selective call receivers
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A pager receiver for receiving signals transmitted in the POCSAG code format which includes a preamble signal followed by at least one batch, the pager receiver including a preamble absence detector circuit for detecting whether or not a received signal includes the preamble and a power saving circuit responsive to the preamble absence detector circuit for deactivating signal processing circuits of the pager receiver as soon as detection is made that the received signal does not include the preamble signal. The power saving circuit causes the signal processing circuits of the pager receiver to operate in a low power mode in which the signal processing circuits are deactivated for an extended period of time, such as for 256 seconds, when a received signal includes an inverted synchronizing signal following the last codeword transmitted, the signal processing circuits being maintained in the low power mode in response to a received signal which includes the preamble signal followed immediately by an inverted synchronizing signal.

Claims

1. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by at least one codeword, the combination comprising power saving circuit means for periodically applying a supply voltage to said signal processing circuits of the receiver, and preamble absence detecting means including first signal detecting circuit means responsive to a received signal to produce a first output signal whenever said received signal fails to have the predetermined code of said preamble signal, second signal detecting circuit means responsive to said received signal to produce a second output signal whenever said received signal fails to have the predetermined code of said preamble signal, signal combining circuit means responsive to said first and second output signals to provide a preamble absence detection signal indicating that the received signal fails to include the predetermined code of said preamble signal, said power saving circuit means responding to said preamble absence detection signal to terminate the supply voltage to said signal processing circuits of the receiver for a predetermined interval of time, said first signal detecting means including first comparing means for comparing said received signal with a first simulated preamble signal, and said second signal detecting means including second comparing means for comparing said received signal with a second simulated preamble signal, said preamble signal of said interrogation signal and said simulated preamble signals being coded to represent a plurality of binary bits occurring in a predetermined sequence, wherein said first and second simulated preamble signals have a 180°

phase relationship to one another.

2. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by at least one codeword, the combination comprising a power saving circuit for periodically applying a supply voltage to said signal processing circuits of the receiver, and preamble absence detecting means including first signal detecting circuit means responsive to a received signal to produce a first output signal whenever said received signal fails to have the predetermined code of said preamble signal, second signal detecting circuit means responsive to said received signal to produce a second output signal whenever said received signal fails to have the predetermined code of said preamble signal, signal combining circuit means responsive to said first and second output signals to provide a preamble absence detection signal indicating that the received signal fails to include the predetermined code of said preamble signal, said power saving circuit responding to said preamble absence detection signal to terminate the supply voltage to said signal processing circuits of the receiver for a predetermined interval of time, said first detecting means includes first comparing means for comparing said received signal with a first simulated preamble signal, and said second detecting means includes second comparing means for comparing said received signal with a second simulated preamble signal, said preamble signal of said interrogation signal and said simulated preamble signals are coded to represent a plurality of binary bits occurring in a predetermined sequence, said first signal detecting means produces said first output signal whenever N-bits of said received signal differ with corresponding bits of said first simulated preamble signal, where N is an integer greater than zero, and said second signal detecting means produces said second output signal whenever N-bits of said received signal differ with corresponding bits of said second simulated preamble signal wherein said first comparing means provides a wrong bit signal each time a bit of said received signal differs with the corresponding bit of said first simulated preamble signal, and said first signal detecting means includes first summing means for producing said first output signal whenever N wrong-bit signals are provided by said first comparing means, and wherein second comparing means provides a wrong bit signal each time a bit of said received signal differs with the corresponding bit of said second simulated preamble signal, and said second signal detecting means includes second summing means for producing said second output signal whenever N wrong-bit signals are provided by said second comparing means.

3. The receiver of claim 2, wherein said first and second summing means comprise first and second binary signal counters, respectively.

4. The receiver of claim 3, wherein said preamble absence detecting means includes reset means for resetting said first and second binary signal counters whenever N+M bits of said received signal compare with corresponding bits of either one of said simulated preamble signals, where M is an integer greater than zero.

5. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by at least one codeword, the combination comprising power saving circuit means for periodically applying a supply voltage to said signal processing circuits of the receiver, and preamble absence detecting means including means for providing first and second simulated preamble signals having said predetermined code of said preamble signal of said interrogate signal and having a predetermined phase relationship to one another and to said preamble signal of said interrogate signal, signal detecting means responsive to a received signal and said simulated preamble signals for producing a preamble absence detection signal indicating that the received signal fails to include the predetermined code of said preamble signal, as soon as detection is made that the received signal fails to correspond to both of said simulated preamble signals, said power saving circuit means responds to said preamble absence detection signal to terminate the supply voltage to the signal processing circuits of the receiver for a predetermined interval of time.

6. The receiver of claim 5, wherein said preamble signal of said interrogation signal and said simulated preamble signals are coded to represent a plurality of binary bits occurring in a predetermined sequence.

7. The receiver of claim 6, wherein said detecting means includes first signal comparing means for producing a first signal whenever N-bits of said received signal differ with corresponding bits of said first simulated preamble signal, where N is an integer greater than zero, and second signal comparing means for producing a second signal whenever N-bits of said received signal differ with corresponding bits of said second simulated preamble signal and means responsive to said first and second signals for producing said preamble absence detection signal.

8. The receiver of claim 5, wherein said signal detecting means includes first comparing means for comparing said received signal with said first simulated preamble signal, and second comparing means for comparing said received signal with said second simulated preamble signal.

9. The receiver of claim 5, wherein said signal processing circuits include first synchronizing signal detecting means for detecting said synchronizing signal portion of said interrogation signal and second synchronizing signal detecting means for detecting the inverse of said synchronizing signal portion of said interrogation signal and producing a control output signal for causing said power saving circuit to terminate the supply voltage to the signal processing circuits of the receiver for an interval of time substantially greater than said predetermined interval of time.

10. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by at least one codeword, the combination comprising a power saving circuit for periodically applying a supply voltage to said signal processing circuits of the receiver, and preamble absence detecting means including means for providing first and second simulated preamble signals having a predetermined phase relationship to one another, signal detecting means responsive to a received signal and said simulated preamble signals for producing a preamble absence detection signal indicating that the received signal fails to include the predetermined code of said preamble signal as soon as detection is made that the received signal fails to correspond to both of said simulated preamble signals, said power saving circuit responding to said preamble absence detection signal to terminate the supply voltage to the signal processing circuits of the receiver for a predetermined interval of time, said preamble signal of said interrogation signal and said simulated preamble signals are coded to represent a plurality of binary bits occurring in a predetermined sequence, said detecting means includes first and second signal comparing means, said first signal comparing means producing a first signal whenever N-bits of said received signal differ with corresponding bits of said first simulated preamble signal, where N is an integer greater than zero, and said second signal comparing means producing a second signal whenever N-bits of said received signal differ with corresponding bits of said second simulated preamble signal and means responsive to said first and second signals for producing said preamble absence detection signal, wherein said first signal comparing means includes a first signal comparing circuit which provides a wrong bit signal each time a bit of said received signal differs with the corresponding bit of said first simulated preamble signal, and first summing means for producing said first signal in response to N wrong-bit signals, and said second comparing means includes a second signal comparing circuit which provides a wrong-bit signal each time a bit of said received signal differs with the corresponding bit of said second simulated preamble signal, and second summing means for producing said second output signal in response to N wrong-bit signals.

11. The receiver of claim 10, wherein said first and second summing means comprise first and second binary signal counters, respectively.

12. The receiver of claim 11, wherein said preamble absence detecting means includes reset means for resetting said first and second binary signal counters whenever N+M bits of said received signal compare with corresponding bits of either one of said simulated preamble signals, where M is an integer greater than zero.

13. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal followed by at least one codeword, said preamble signal being coded to represent a plurality of binary bits occurring in a predetermined sequence, the combination comprising power saving circuit means for periodically applying a supply voltage to said signal processing circuits, and preamble absence detecting means including means for providing first and second simulated preamble signals, each of said simulated preamble signals being binary coded signals having bits occurring in said predetermined sequence for the bits of said preamble signal, said first and second simulated preamble signals having a predetermined phase relationship to one another and to said preamble signal of said interrogate signal, first signal comparing means responsive to a received signal and said first simulated preamble signal to produce a first output signal whenever N-bits of said received signal fail to compare with corresponding bits of said first simulated preamble signal, where N is an integer greater than zero, second signal comparing means responsive to said received signal and said second simulated preamble signal to produce a second output signal whenever N-bits of said received signal fail to compare with corresponding bits of said second simulated preamble signal, signal combining circuit means responsive to said first and second output signals to provide a preamble absence detection signal indicating that the received signal fails to include the preamble signal, said power saving circuit means responding to said preamble absence detection signal to terminate the supply voltage to said signal processing circuits of the receiver for a predetermined interval of time.

14. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal followed by at least one codeword, said preamble signal being coded to represent a plurality of binary bits occurring in a predetermined sequence, the combination comprising a power saving circuit for periodically applying a supply voltage to said signal processing circuits, and preamble absence detecting means including means for providing first and second simulated preamble signals, each of said simulated preamble signals being binary coded signals having bits occurring in said predetermined sequence for the bits of said preamble signal, said first and second simulated preamble signals having a predetermined phase relationship to one another, first signal comparing means responsive to a received signal and said first simulated preamble signal to produce a first output signal whenever N-bits of said received signal differ with corresponding bits of said first simulated preamble signal, where N is an integer greater than zero, second signal comparing means responsive to said received signal and said second simulated preamble signal to produce a second output signal whenever N-bits of said received signal differ with corresponding bits of said second simulated preamble signal, signal combining circuit means responsive to said first and second output signals to provide a preamble absence detection signal indicating that the received signal fails to include the preamble signal, said power saving circuit responding to said preamble absence detection signal to terminate the supply voltage to said signal processing circuits of the receiver for a predetermined interval of time, wherein said first signal comparing means includes a first signal comparing circuit which provides a wrong-bit signal each time a bit of said received signal differs with the corresponding bit of said first simulated preamble signal, and first binary signal counting means for counting the number of wrong-bit signals provided by said first signal comparing circuit and producing said first signal when N wrong-bit signals have been provided, and said second comparing means includes a second signal comparing circuit which provides a wrong-bit signal each time a bit of said received signal differs with the corresponding bit of said second simulated preamble signal, and second binary signal counting means for counting the number of wrong-bit signals provided by said second signal comparing circuit and producing said second output signal when N wrong-bit signals have been provided.

15. The receiver of claim 14, wherein said preamble absence detecting means includes reset means for resetting said first and second binary signal counters whenever N+M bits of said received signal compare with corresponding bits of either one of said simulated preamble signals, where M is an integer greater than zero.

16. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by one or more batches of a predetermined time duration and each batch including a synchronizing signal and a plurality of information signals, said signal processing circuits processing a received signal and producing a processed signal including the code of said preamble signal, and first synchronizing signal detecting means responsive to the synchronizing signal to synchronize the operation of the receiver, the combination comprising power saving circuit means for periodically providing a supply voltage to render said signal processing circuits operative to process the received signal, and absence detecting means having an input coupled to said signal processing circuits and having an output coupled to said power saving circuit means, said absence detecting means including means for detecting whether or not said processed signal includes the predetermined code of said preamble signal and for terminating the supply voltage as soon as detection is made that said processed signal does not include said predetermined code, and second synchronizing signal detecting means responsive to an inverted synchronizing signal which is the complement of said synchronizing signal for causing the power saving circuit means to deactivate the signal processing circuits of the receiver for an interval of time that is greater than the duration of one of said batches.

17. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by one or more batches of a predetermined time duration and each batch including a synchronizing signal and a plurality of address signals, the signal processing circuits including first synchronizing signal detecting means, address means, and power saving circuit means including timing means for operating the signal processing circuits in a power saving mode in which the signal processing circuits are activated periodically for a time interval of a predetermined duration for detecting the preamble signal and the synchronizing signal, the first synchronizing signal detecting means being responsive to a synchronizing signal to cause the power saving circuit means to deactivate the signal processing circuits and subsequently reactivate the signal processing circuits at a preselected time following the occurrence of the synchronizing signal for enabling the address means to respond to address signals, the combination comprising preamble absence detecting means responsive to a received signal for producing a preamble absence detection signal whenever the received signal fails to include the predetermined coding of said preamble signal, the power saving circuit means responding to said preamble absence detection signal to deactivate the signal processing circuits of the receiver for a predetermined interval of time, and in the absence of said preamble absence detection signal, the power saving circuit means maintaining the signal processing circuits activated for detecting the synchronizing signal, and second synchronizing signal detecting means responsive to an inverted synchronizing signal which is the complement of said synchronizing signal for causing the power saving circuit means to deactivate the signal processing circuits of the receiver for an interval of time substantially greater than the interval of time of one of said batches.

18. The receiver of claim 17, wherein the inverted synchronizing signal is transmitted following the address signals.

19. The receiver of claim 17, wherein the inverted synchronizing signal is transmitted following the preamble signal.

20. The receiver of claim 17, wherein said preamble absence detecting means includes means for providing first and second simulated preamble signals having a predetermined phase relationship to one another, and signal detecting means responsive to a received signal and said simulated preamble signals for producing said preamble absence detecting signal whenever the received signal fails to correspond to both of said simulated preamble signals.

21. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal followed by a synchronizing signal and a plurality of address signals, said signal processing circuits including preamble detecting means, first synchronizing signal detecting means, address signal detecting means, and power saving circuit means including timing means for operating the signal processing circuits in a first power saving mode in which the signal processing circuits are activated periodically for a given time interval of a predetermined duration for detecting the preamble signal and the synchronizing signal, the first synchronizing signal detecting means upon detecting a synchronizing signal causing the power saving circuit means to operate the signal processing circuits in a second power saving mode in which the signal processing circuits are deactivated and subsequently reactivated at a preselected time following the occurrence of the synchronizing signal for enabling the address signal detecting means to detect address signals, the improvement comprising a second synchronizing signal detecting means for detecting an interrogate signal including a preamble signal followed by an inverted synchronizing signal which is the complement of the synchronizing signal and responsively producing a power-down signal, the power saving circuit means responding to said power-down signal to cause the signal processing circuits to operate in a third power saving mode in which the signal processing circuits are maintained deactivated for a time interval which is substantially greater than said predetermined time interval and subsequently are reactivated periodically for detecting said interrogate signal and said signal processing circuits responding to the detection of at least a portion of said preamble signal followed immediately by said inverted synchronizing signal to produce a further power-down signal, the power saving circuit means maintaining the signal processing circuits operating in said third power saving mode as long as said further synchronizing signal detecting means continues to detect at least a portion of said preamble signal followed immediately by an inverted synchronizing signal each time the signal processing circuits are reactivated when operating in said third power saving mode, and the power saving circuit means causing the operation of the signal processing circuits to revert to said first power saving mode if said second synchronizing signal detecting means fails to detect an inverted synchronizing signal when the signal processing circuits are reactivated when operating in said third power saving mode.

22. The receiver of claim 21, wherein the power saving circuit means causes the operation of the signal processing circuits to revert to said second power saving mode for detecting address signals in response to the detection of a synchronizing signal by the first synchronizing signal detecting means while the signal processing circuits are operating in said third power saving mode.

23. The receiver of claim 22, wherein the power saving circuit means causes the operation of the signal processing circuits to revert from said second power saving mode to said third power saving mode in response to the detection of an inverted synchronizing signal which is received after said address signals have been detected.

24. The receiver of claim 21, wherein an inverted synchronizing signal is transmitted immediately following the address signals to cause the signal processing circuits to operate in said third power saving mode.

25. The receiver of claim 24, wherein an inverted synchronizing signal is transmitted immediately following the preamble signal to maintain the signal processing circuits operating in said third power saving mode.

26. The receiver of claim 25, wherein said preamble signal, said synchronizing signal and said inverted synchronizing signal each are coded to represent a plurality of binary bits occurring in a predetermined sequence, and wherein the power saving circuit reactivates the signal processing circuits at a predetermined time following the detection of said inverted synchronizing signal whereby the preamble detecting means is enabled to detect only a portion, corresponding to N-bits, of the preamble signal which immediately precedes a subsequently received inverted synchronizing signal.

27. The receiver of claim 25, wherein the preamble detecting means includes means for producing an output signal for indicating that N-bits of the preamble signal of a received signal have been detected, and said power saving circuit means responding to said output signal to maintain the signal processing circuits activated for detecting said subsequently received inverted synchronizing signal.

28. The receiver of claim 21, wherein the power saving circuit means deactivates the signal processing circuits before the end of said predetermined time interval whenever the preamble detecting means fails to detect a preamble signal.

29. The receiver of claim 21, wherein the ratio of the time that the signal processing circuits are deactivated to the time that the signal processing circuits are activated is in the range of 1350 to 1365.

30. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal coded to represent an N-bit binary signal followed by a synchronizing signal coded to represent an M-bit binary signal and a plurality of address signals each coded to represent a multi-bit binary signal, said signal processing circuits including preamble detecting means, synchronizing signal detecting means, address signal detecting means, and power saving circuit means including timing means for operating the signal processing circuits in a first power saving mode in which the signal processing circuits are activated periodically for a given time interval of a predetermined duration for detecting the preamble signal and the synchronizing signal, and a second power saving mode in which the signal processing circuits are deactivated and subsequently reactivated at a preselected time following the occurrence of the synchronizing signal for detecting address signals, the improvement comprising a further synchronizing signal detecting means for responding to an M-bit binary signal which is received immediately following said address signals and which represents an inverted synchronizing signal for causing the power saving circuit means to operate the signal processing circuits in a third power saving mode in which the signal processing circuits are maintained deactivated for a time interval substantially greater than said predetermined time interval and thereafter reactivated periodically for detecting an interrogate signal, said signal processing circuits responding to detection of at least a portion of the N-bit preamble signal followed immediately by an M-bit inverted synchronizing signal for maintaining said signal processing circuits operating in said third mode.

31. The receiver of claim 30, wherein the power saving circuit means causes the operation of the signal processing circuits to revert to said first mode whenever said further synchronizing signal detecting means fails to detect an M-bit binary signal representing an inverted synchronizing signal when the signal processing circuits are rectivated when operating in said third power saving mode.

32. The receiver of claim 30, wherein the power saving circuit means causes the operation of the signal processing circuits to revert directly to said second power saving mode for detecting address signals in response to the detection of an M-bit synchronizing signal by the synchronizing signal detecting means while the signal processing circuits are operating in said third power saving mode.

33. The receiver of claim 32, wherein the power saving circuit means causes the operation of the signal processing circuits to revert from said second power saving mode directly to said third power saving mode in response to the detection of an M-bit inverted synchronizing signal which is received after said address signals have been detected.

34. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal having a predetermined code followed by a synchronizing signal, said signal processing circuits processing a received signal and producing a processed signal including the code, and synchronizing means responsive to the synchronizing signal to synchronize the operation of the receiver, the combination comprising a power saving circuit for periodically providing a supply voltage to render said signal processing circuits operative to process the received signal, and absence detecting means having an input coupled to said signal processing circuits and having an output coupled to said power saving circuit, said absence detecting means including means for detecting whether or not said processed signal includes the predetermined code of said preamble signal and for terminating the supply voltage as soon as detection is made that said processed signal does not include said predetermined code, and a further synchronizing signal detecting means responsive to a synchronizing signal which is the complement of said synchronizing signal for causing the power saving circuit to deactivate the signal processing circuits of the receiver for an interval of time.

35. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by one or more batches of a predetermined time duration and each batch including a synchronizing signal and a plurality of information signals, said signal processing circuits processing a received signal and producing a processed signal including the code, and synchronizing signal detecting means responsive to the synchronizing signal to synchronize the operation of the receiver, the combination comprising a power saving circuit for periodically providing a supply voltage to render said signal processing circuits operative to process the received signal, and absence detecting means having an input coupled to said signal processing circuits and having an output coupled to said power saving circuit, said absence detecting means including means for detecting whether or not said processed signal includes the predetermined code and for terminating the supply voltage as soon as detection is made that said processed signal does not include said predetermined code, and further synchronizing signal detecting means responsive to an inverted synchronizing signal which is the complement of said synchronizing signal for causing the power saving circuit to deactivate the signal processing circuits of the receiver for an interval of time that is greater than the duration of one of said batches.

36. In a selectively addressable receiver having signal processing circuits for receiving an interrogation signal including a preamble signal having a predetermined code followed by one or more batches of a predetermined time duration and each batch including a synchronizing signal and a plurality of information signals, said signal processing circuits processing a received signal and producing a processed signal including the code, and synchronizing signal detecting means responsive to the synchronizing signal to synchronize the operation of the receiver, the combination comprising a power saving circuit for periodically providing a supply voltage to render said signal processing circuits operative to process the received signal, and absence detecting means having an input coupled to said signal processing circuits and having an output coupled to said power saving circuit, said absence detecting means including means for detecting whether or not said processed signal includes the predetermined code of said preamble signal and for terminating the supply voltage as soon as detection is made that said processed signal does not include said predetermined code, and further synchronizing signal detecting means responsive to a synchronizing signal which is the complement of said synchronizing signal for causing the power saving circuit to deactivate the signal processing circuits of the receiver for an interval of time that is greater than the duration of one of said batches.

37. A method for providing a battery saving function for a battery powered personal communications receiver which receives an interrogation signal including one or more batches of a predetermined time duration, each batch including a synchronizing signal and a plurality of coded message information signals, the receiver being powered during a first periodically occurring time interval of a predetermined duration for receiving synchronizing signals, and during at least one time interval of a plurality of additional predetermined time intervals following the occurrence of the synchronizing signal and to which the receiver is assigned, for receiving coded message information signals, said method comprising the steps of

applying power to said receiver to enable said receiver to receive synchronizing signals including a first coded synchronizing signal that is generated and transmitted to said receiver when coded message information signals are to be transmitted in at least one of the plurality of additional time intervals and a second coded synchronizing signal that is generated and transmitted to said receiver in place of the first synchronizing signal when coded information message signals are not to be transmitted in any of the plurality of additional time intervals;

maintaining said receiver in synchronization with the system when either the first or second synchronizing signals are received by said receiver; and

suspending the supply of power to the receiver immediately following the receipt of the second synchronizing signal,

whereby the supply of power to the receiver is suspended for an extended interval of time during which coded information message signals are not to be transmitted, the duration of said extended interval of time being greater than the duration of one batch.

38. A personal communications receiver which receives an interrogation signal including one or more batches of a predetermined time duration, each batch including a synchronizing signal and a plurality of coded message information signals, said receiver being powered during a first periodically occurring time interval of a predetermined duration for receiving synchronizing signals, and during at least one time interval of a plurality of additional predetermined time intervals following the synchronizing signal and to which the receiver is assigned for receiving coded message information signals, a first coded synchronizing signal being transmitted when coded message information signals are to be transmitted in at least one of the plurality of additional predetermined time intervals, and a second coded synchronizing signal being transmitted in place of said first synchronizing signal when coded message information signals are not to be transmitted in any of the plurality of additional time intervals, said receiver comprising

battery powered signal receiver circuits for receiving and detecting the transmitted coded synchronizing and coded message information signals,

means responsive to said received coded synchronizing signals for maintaining receiver synchronization, and power saving circuit means for supplying power to said receiver for the additional time interval for receiving coded message information signals when the first synchronizing signal is received, and for suspending the supply of power to said receiver for an extended interval of time when said second synchronizing signal is received, said extended interval of time being greater than the duration of one batch.