Method of and apparatus for inspecting pattern on printed board

• US 5,384,711 A
• Filed: 11/12/1991
• Issued: 01/24/1995
• Est. Priority Date: 11/27/1990
• Status: Expired due to Fees

• Current Assignee: SCREEN Holdings Co., Ltd.
• Original Assignee: SCREEN Holdings Co., Ltd.
• Inventors: Kanai, Takao, Sezaki, Yoshinori, Atsuta, Hitoshi, Mandai, Ichirou
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/791,063
• Time in Patent Office: 1,169 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/552, 382/8
• US Class Current: 716/112
• CPC Class Codes: G06T 2207/30141 Printed circuit board [PCB]
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/60 Analysis of geometric attributes

Abstract

In order to correctly detect the width of wiring pattern on a printed board, a multiple train operator applied to image data. The multiple train operator consists of arms each having three unit arms. The binary data obtained by applying the multiple train operator to the image data is converted into a single horizontal arm and a single vertical arm. The combination of the horizontal and vertical arms corresponds to a single cross operator. The conversion into the single cross operator form is conducted through a logical operation on the binary data obtained by the multiple train operator, so that quantization errors are compensated and fine pattern defects can be detected. As a result, the width of the wiring pattern etc. are correctly obtained.

Claims

1. A method of inspecting a wiring pattern formed on a printed board, comprising the steps of:

(a) obtaining an image of said wiring pattern;

(b) applying an image operator to said image to obtain a first data array, wherein said image operator has a plurality of operator arms each of which is formed of a plurality of pixel trains, and said first data array has a first plurality of data arms each of which is formed of a plurality of trains of data values, said step of applying an image operator including the steps of;

(b-1) defining said image operator so that said plurality of pixel trains form a close bundle of parallel pixel trains;

(b-2) serially selecting each pixel on said image; and

(b-3) applying said image operator to said image while adjusting a center of said image operator to said each pixel of said image; and

(c) converting said first data array into a second data array having a second plurality of data arms each of which is formed of a single train of data values, said converting step including the step of applying a logical operation on said plurality of trains of data values to obtain said single train of data values by;

(c-1) determining a first type of logical operation and a second type of logical operation;

(c-2) obtaining a data value of said image data at a center of said first data array which corresponds to said center of said image operator;

(c-3) selecting one of said first and second types of logical operation as a function of said data value at said center of said first data array; and

(c-4) applying said one of said first and second types of logical operation to said plurality of trains of data values to obtain said single train of data values; and

(d) inspecting said wiring pattern as a function of said second data array.

2. The method of claim 1, wherein

the step (b-1) comprises the step of:

(b-1-1) defining said image operator so that said plurality of operator arms cross each other at said center of said image operator.

3. The method of claim 2, wherein

the step (b-1-1) comprises the step of:

defining said image operator so that said plurality of operator arms form a radial pattern.

4. The method of claim 2, wherein

the step (d) comprises the steps of:

(d-1) detecting a number of pixels which are aligned along an elongated direction of each arm in said second plurality of data arms and which have a same logical level; and

(d-2) comparing said number of pixels with a threshold number to inspect said wiring pattern.

5. The method of claim 1, wherein

the step (c-1-4) comprises the step of:

applying said one of said first and second types of logical operation to each chain of pixel data values aligning in said plurality of data arms in respective directions traversing said plurality of data arms.

6. An apparatus for inspecting a wiring pattern formed on a printed board, comprising:

(a) first means for obtaining an image of said wiring pattern;

(b) second means for applying an image operator to said image to obtain a first data array, wherein said image operator has a plurality of operator arms each of which is formed of a plurality of pixel trains, and said first data array has a first plurality of data arms each of which is formed of a plurality of trains of data values, said second means including;

(b-1) means for holding said image operator so that said plurality of pixel trains form a close bundle of parallel pixel trains; and

(b-2) means for serially selecting each pixel on said image; and

(b-3) means for delivering said image data to said means (b-1) to apply said image operator to said image while adjusting a center of said image operator to said each pixel of said image;

(c) third means for converting said first data array into a second data array having a second plurality of data arms each of which is formed of a single train of data values, said third means applying a logical operation to said plurality of trains of data values to obtain said single train of data values and comprising;

(c-1) means for obtaining a data value of said image data at a center of said first data array which corresponds to said center of said image operator;

(c-2) means for selecting one first and second types of logical operation as a function of said data value at said center of said first data array; and

(c-3) means for applying said one of said first and second types of logical operation to said plurality of trains of data values to obtain said single train of data values; and

(d) fourth means for inspecting said wiring pattern as a function of said second data array.

7. The apparatus of claim 6, wherein

said means (b-1) comprises:

(b-1-1) means for holding said image operator so that said plurality of operator arms cross each other at said center of said image operator.

8. The apparatus of claim 7, wherein

said means (b-1-1) comprises:

means for holding said image operator so that said plurality of operator arms form a radial pattern.

9. The apparatus of claim 6, wherein

said means (c-1-3) comprises:

means for applying said one of said first and second types of logical operation to each chain of pixel data values aligning in said plurality of data arms in respective directions traversing said plurality of data arms.

10. The apparatus of claim 9, wherein

said means (d) comprises:

(d-1) means for detecting a number of pixels which are aligned along an elongated direction of each arm in said second plurality of data arms and which have a same logical level; and

(d-2) means for comparing said number of pixels with a threshold number to inspect said wiring pattern.