Synchronous semiconductor memory device

• US 5,384,745 A
• Filed: 04/14/1993
• Issued: 01/24/1995
• Est. Priority Date: 04/27/1992
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kajimoto, Takeshi, Konishi, Yasuhiro, Miyamoto, Takayuki, Iwamoto, Hisashi
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/046,333
• Time in Patent Office: 650 Days
• Field of Search: 365/194, 365/195, 365/230.03, 365/233, 365/230.05, 365/221, 365/189.12, 365/189.04, 365/193
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

Claims

1. A synchronous semiconductor memory device taking in control signals and external signals including address signals having bank addresses and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other in accordance with the bank addresses included in the address signals, and one of the bank addresses designating one of the banks;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank; and

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank,

wherein a data read or write operation is performed only for the one of the banks designated by the one of the bank addresses.

4. The synchronous semiconductor memory device according to claim 1, further comprising a data input terminal for receiving input data to be written, and wherein said plurality of write register means are selectively coupled to said data input terminal.

5. The synchronous semiconductor memory device according to claim 4, wherein each of said plurality of write register means includes a plurality of registers for storing the input data successively in a predetermined order.

6. The synchronous semiconductor memory device according to claim 1, further comprising a data output terminal for supplying an external data, and wherein said plurality of read register means are selectively coupled to said data output terminal.

7. The synchronous semiconductor memory device according to claim 6, wherein each of said read register means includes a plurality of read registers successively coupled to said data output terminal.

10. The synchronous semiconductor memory device according to claim 1,

selection means responsive to an address for selecting a memory cell in said memory cell array;

delay means for delaying a timing of activating the selection means in a data writing operation mode with respect to the timing of activation in a data reading operation mode.

13. The synchronous semiconductor memory device according to claim 1, wherein each of said bank includes:

a plurality of memory cells arranged in rows and columns,

a plurality of word lines arranged corresponding to the rows for connecting memory cells on a corresponding row,

a plurality of pairs of bit lines arranged corresponding to the columns for connecting memory cells on a corresponding column,

a data line for transmitting data to and from a selected memory cell,

column decode means responsive to an address signal for generating column selecting signal for selecting a column among the columns,

connecting means responsive to the column selecting signal for connecting only one bit line of a pair of bit lines corresponding to the column selected by said column selecting signal.

14. The synchronous semiconductor memory device according to claim 13, further comprising

an amplifier means including a first node and a second node for differentially amplifying signal potentials on the first and second nodes in response to an activation signal,

equalizing means for equalizing the signal potentials on said first and second nodes before activation of said amplifier means, and

coupling means for connecting said one data line to said first node after inactivation of said equalizing means and before the activation of the amplifier means.

16. The synchronous semiconductor memory device according to claim 1, further comprising:

state decode means for decoding control signals and an address signal applied in synchronization with said clock signal to activate independently one of the plurality of banks for memory cell selection.

2. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

data input/output number setting means for setting the number of data which can be input or output at one time; and

bank number setting means responsive to information of the data input/output number set by said data input/output number setting means for setting an upper limit of the number of said plurality of banks.

3. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

wrap length setting means for setting a wrap length indicating the number of bits which can be successively read and written by one-time designation of an address; and

bank number setting means for setting an upper limit of the number of said banks in accordance with information of the wrap length set by said wrap length setting means.

8. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

a data input terminal for receiving input data to be written, and wherein said plurality of write register means are selectively coupled to said data input terminal;

mask registers provided corresponding to said plurality of write registers and successively coupled in a first predetermined order to a mask terminal, said mask registers receiving and storing mask data supplied in parallel with the input data to be written; and

transfer inhibition means responsive to the mask data stored in said mask registers for inhibiting data transfer from a corresponding write register to a selected memory cell,

wherein each of said plurality of write register means includes a plurality of registers for storing the input data successively in a second predetermined order.

9. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

a data input terminal for receiving input data to be written, and wherein said plurality of write register means are selectively coupled to said data input terminal;

bank selection means responsive to a bank address for enabling a bank designated by the bank address among said plurality of banks;

selection means responsive to an address for selecting a predetermined number of memory cells at a time in the bank enabled by said bank selection means;

register selection means responsive to a write permit signal and the address for successively selecting and coupling the write registers to said data input terminal;

detecting means responsive to said clock signal and the write permit signal for detecting a completion of writing the predetermined number of data into said write registers; and

data writing means, responsive to the detecting means detecting the completion of writing the predetermined number of data, or to both non-detection of the completion of writing and transition of said write permit signal to an inactive state, for writing data in said write registers to corresponding memory cells in said selected memory cells.

11. The synchronous semiconductor memory device according to claim 9, further comprising,

means for storing a wrap data indicating the number of data to be successively supplied to be written into memory cells,

determining means responsive to the wrap data for determining whether or not the number of data indicated by the wrap data are supplied,

control means responsive to said determining means for repeatedly enabling said selection means and said data writing means until said determining means determines that the indicated number of data are successively supplied.

12. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

means for taking in a row address strobe signal instructing a strobing of a row address signal and a start of a row selection operation, in response to said clock signal for generating a first internal row address strobe signal, said memory cells arranged in rows and columns and said row address designating a row in said rows;

means responsive to said clock signal and said row address strobe signal for generating a second internal row address strobe signal at an earlier timing than generation of said first internal row address strobe signal;

means responsive to said second row address strobe signal for taking in the row address signal to generate an internal row address signal; and

means responsive to said first internal row address strobe signal for activating the row selection operation.

15. A synchronous semiconductor memory device taking in control signals and external signals including address signals and input data in synchronization with a clock signal in a form of a series of pulses, comprising:

a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other;

a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank;

a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank;

first control means for taking in a clock buffer activating signal in asynchronization with said clock signal, and for generating a first control signal;

first clock buffer means responsive to said first control signal for generating a first internal clock signal synchronous with said clock signal;

second control means for taking in the clock buffer activating signal in synchronization with said first internal clock signal and for generating a second control signal;

third control means responsive to a predetermined operation mode designating signal for activating said first control means and inactivating said second control means;

second clock buffer means responsive to said second control signal for generating a second internal clock signal synchronous with said clock signal; and

means responsive to said second internal clock signal for controlling data writing operating and data reading operation such that operations of said data writing and reading are suspended when no second clock signal is generated.

17. A semiconductor memory device operable to take in a signal in synchronization with a clock signal in a form of a series of pulses, comprising:

a plurality of data terminals for receiving and transmitting data;

a plurality of memory banks having bank addresses, each including a plurality of memory cells arranged in rows and columns;

a plurality of groups of data holding means provided corresponding to the plurality of memory banks for communicating data with said plurality of memory cells, each of said plurality of groups of data including a plurality of data holding means for each of said plurality of data terminals; and

means responsive to one of the bank addresses for activating one of the memory banks designated by said one of the bank addresses for memory cell selection and for activating a corresponding group of the plurality of groups of data holding means,

wherein each of said plurality of bank addresses designate each of the plurality of memory banks for activation using externally applied bank address signals.

18. A semiconductor memory device according to claim 17, further comprising means for sequentially coupling data holding means of said corresponding group to associated data terminals.

19. A randomly accessible semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns;

memory selection means responsive to an address signal for selecting memory cells in an array;

a data terminal;

a plurality of read data registers for receiving and holding data read from the selected memory cells, and

a plurality of write registers for holding data to be written into the selected memory cells, said plurality of write registers being provided separately from said plurality of read data registers, and one of said plurality of read data registers and said write registers being coupled to said data terminal for data communication.

21. A randomly accessible semiconductor memory device according to claim 19,

wherein said memory cell array includes banks having bank addresses activated for memory cell selection independent from each other in accordance one of the bank addresses designated by the address signal, and

wherein a data read or write operation is performed only for the one of the banks designated by the bank address signal.

22. A randomly accessible semiconductor memory device according to claim 19, wherein the address signal is applied in synchronization with a clock signal to independently activate the one of the banks for one of reading and write data.

20. A semiconductor memory device, comprising:

a plurality of read terminals for supplying read-out data bits in parallel;

a plurality of write terminals for receiving write-in data bits in parallel;

a plurality of banks each having a bank address and including

(a) a memory cell array including a plurality of memory cells arranged in rows and columns;

(b) a plurality of groups of read registers provided corresponding to respective read terminals, each of said groups including a plurality of registers for holding data;

(c) a plurality of groups of write registers provided corresponding to respective write terminals, each of said group including a plurality of registers for holding data;

(d) memory selection means responsive to an address signal for selecting a plurality of memory cells in said memory cell array at one time;

(e) read means responsive to a read enable signal for reading data bits from the selected memory cells into said registers of each said group of read registers;

(f) write means responsive to a write enable signal for writing data bits into said selected memory cells from said registers of each said group of write registers;

(g) read selection means responsive to the address signal and the read enable signal for coupling the registers of each said group of read registers to corresponding read terminals in a predetermined order;

(h) write selection means responsive to the write enable signal and the address signal for coupling the registers of each of said groups of write registers to corresponding write terminals in a predetermined order; and

(i) bank selection means responsive to a bank address signal for enabling one of the plurality of banks independent of each other.