Semiconductor memory device comprising a test circuit and a method of operation thereof

• US 5,384,784 A
• Filed: 08/27/1991
• Issued: 01/24/1995
• Est. Priority Date: 08/29/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mori, Shigeru, Miyamoto, Hiroshi, Morooka, Yoshikazu, Kinoshita, Mitsuya, Suwa, Makoto, Kikuda, Shigeru
• Primary Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/750,040
• Time in Patent Office: 1,246 Days
• Field of Search: 307/530, 330/257, 364/579, 364/580, 371/21.1, 371/25.1
• US Class Current: 714/718
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

Claims

1. A semiconductor memory device comprising:

a memory array including a plurality of memory cells arranged in a plurality of rows and columns, said plurality of columns of said memory cell array divided into a plurality of groups in an interleaved manner;

selecting means for simultaneously selecting all columns in each group in a selected row during testing operation,

reading means for reading data stored in the memory cells of the selected rows and columns;

a plurality of test means corresponding respectively to said plurality of groups;

each of said plurality of test means simultaneously comparing data read out from said selecting columns belonging to the corresponding group with a predetermined expected data value; and

indicating means for providing a result of said plurality of test means, wherein

said selecting means comprises means for selecting a single one of said plurality of columns in each group during a normal non-tested operation,

each of said plurality of test means comprises

a plurality of first amplifying means corresponding respectively to said plurality of columns,

second amplifying means, and

expected data input means for storing an expected data value,

the first amplifying means corresponding to the column selected by said selecting means and said second amplifying means form a current mirror type amplifier during normal reading operation, and

each of the first amplifying means corresponding to the columns selected by said selecting means compares data read out from the corresponding column with the expected data value during a testing operation.

2. The semiconductor memory device according to claim 1, further comprising:

a plurality of write buses corresponding respectively to said plurality of groups,

a plurality of read buses corresponding respectively to said plurality of group,

connecting means for connecting a single column selected by said selecting means in each block to the corresponding write bus during normal writing operation, and

activation means for activating the first amplifying means corresponding to a column selected by said selecting means.

3. The semiconductor memory device according to claim 1, wherein each of said plurality of test means carries out line mode testing.

4. A semiconductor memory device comprising:

a memory array including a plurality of word lines, a plurality of bit line pairs provided to cross said plurality of word lines, and a plurality of memory cells provided at crossings of said word lines and said bit line pairs said plurality of bit line pairs divided into a plurality of groups in an interleaved manner,

a plurality of write buses corresponding respectively to said plurality of groups,

a plurality of read buses corresponding respectively to said plurality of groups,

a plurality of first amplifying means each provided between each of said plurality of bit line pairs and a corresponding read bus,

a plurality of second amplifying means corresponding respectively to said plurality of groups,

a plurality of expected data input means corresponding respectively to said plurality of groups for storing an expected data value,

selecting means for selecting a single one of said plurality of bit line pairs in each group for reading and writing during normal operation, and for simultaneously selecting all bit line pairs in each group during testing operation,

connecting means for connecting a bit line pair selected by said selecting means to a corresponding write bus during normal operation, and

activation means for activating a first amplifying means corresponding to a selected bit line pair,

wherein the activated first amplifying means and said second amplifying means form a current mirror type amplifier during normal reading operation, and

wherein each of the activated first amplifying means compares data of the corresponding bit line pair with a corresponding expected data value for providing the comparison result thereof to the corresponding read bus during testing operation.

5. The semiconductor memory device according to claim 4, further comprising

a plurality of error detection means corresponding respectively to said plurality of groups for providing an error flag in response to a comparison indication received from the corresponding first amplifying means.

6. The semiconductor memory device according to claim 4, wherein each of said plurality of first amplifying means forms a differential amplifier.

7. The semiconductor memory device according to claim 4, wherein said selecting means comprises column decoder means responsive to an externally applied address signal for generating a plurality of selecting signals for simultaneously selecting all bit line pairs in each group during testing operation and for generating a single selecting signal for selecting a bit line pair in each group during normal reading and writing operation.

8. The semiconductor memory device according to claim 4, wherein said test operation comprises a line mode test operation.

9. The semiconductor memory device according to claim 4, further comprising:

a plurality of third amplifying means corresponding respectively to said plurality of bit line pairs for amplifying potential difference on the corresponding bit line pair, and control means for activating said third amplifying means at the time of reading and writing of normal operation, and for inactivating temporarily said third amplifying means and then activating again third amplifying means at the time of writing of test operation.

10. The semiconductor memory device according to claim 9, further comprising:

equalized means for equalizing the potentials of said plurality of bit line pairs during the period when said plurality of amplifying means are inactivated by said control means at the time of writing of test operation.

11. The semiconductor memory device according to claim 4, further comprising:

a plurality of data buses corresponding respectively to said plurality of groups,

a plurality of line test buses corresponding respectively to said plurality of groups, and

a plurality of switch means corresponding respectively to said plurality of groups, wherein each of said plurality of switch means connects a corresponding read bus to a corresponding data bus during normal reading operation and connects a corresponding read bus to a corresponding line test bus during testing operation.

12. The semiconductor memory device according to claim 11, wherein said test operation comprises a line mode test operation.

13. The semiconductor memory device according to claim 11, further comprising

setting means for setting said semiconductor memory device to a normal operation mode or a test operation mode.

14. The semiconductor memory device according to claim 13, wherein said setting means comprises

an external terminal for receiving an external signal, and

detection means for generating a signal for setting said semiconductor memory device to a test mode, when a voltage of a level higher than a normal logic level is applied to said external terminal.

15. The semiconductor memory device according to claim 4, wherein each of said plurality of second amplifying means forms a differential amplifier.

16. The semiconductor memory device according to claim 15, wherein said differential amplifier comprises a symmetric type differential amplifier.

17. The semiconductor memory device according to claim 15, wherein said differential amplifier comprises a double differential amplifier.

18. The semiconductor memory device according to claim 15, wherein said differential amplifier comprises a double symmetric type differential amplifier.

19. A semiconductor memory device comprising:

first and second memory arrays including a plurality of memory cells arranged in a plurality of rows and columns, said plurality of columns of said memory cell array divided into a plurality of groups in an interleaved manner;

switching means for selecting one of said first and second memory arrays;

selecting means for simultaneously selecting all columns in each group in a selected row in the selected memory array during testing operation;

reading means for reading data stored in the memory cells of the selected row and columns;

a plurality of test means corresponding respectively to said plurality of groups;

each of said plurality of test means simultaneously comparing data read out from said selected columns belonging to the corresponding group with a predetermined expected data value; and

indicating means for providing a result of said plurality of test means, wherein

said selecting means comprises means for selecting a single one of said plurality of columns in each group during a normal non-tested operation,

each of said plurality of test means comprises

a plurality of first amplifying means corresponding respectively to said plurality of columns,

second amplifying means, and

expected data input means for storing an expected data value,

the first amplifying means corresponding to the column selected by said selecting means and said second amplifying means form a current mirror type amplifier during normal reading operation, and

each of the first amplifying means corresponding to the columns selected by said selecting means compares data read out from the corresponding column with the expected data value during a testing operation.