Semiconductor memory device comprising a test circuit and a method of operation thereof
First Claim
1. A semiconductor memory device comprising:
- a memory array including a plurality of memory cells arranged in a plurality of rows and columns, said plurality of columns of said memory cell array divided into a plurality of groups in an interleaved manner;
selecting means for simultaneously selecting all columns in each group in a selected row during testing operation,reading means for reading data stored in the memory cells of the selected rows and columns;
a plurality of test means corresponding respectively to said plurality of groups;
each of said plurality of test means simultaneously comparing data read out from said selecting columns belonging to the corresponding group with a predetermined expected data value; and
indicating means for providing a result of said plurality of test means, whereinsaid selecting means comprises means for selecting a single one of said plurality of columns in each group during a normal non-tested operation,each of said plurality of test means comprisesa plurality of first amplifying means corresponding respectively to said plurality of columns,second amplifying means, andexpected data input means for storing an expected data value,the first amplifying means corresponding to the column selected by said selecting means and said second amplifying means form a current mirror type amplifier during normal reading operation, andeach of the first amplifying means corresponding to the columns selected by said selecting means compares data read out from the corresponding column with the expected data value during a testing operation.
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Accused Products
Abstract
A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
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Citations
19 Claims
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1. A semiconductor memory device comprising:
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a memory array including a plurality of memory cells arranged in a plurality of rows and columns, said plurality of columns of said memory cell array divided into a plurality of groups in an interleaved manner; selecting means for simultaneously selecting all columns in each group in a selected row during testing operation, reading means for reading data stored in the memory cells of the selected rows and columns; a plurality of test means corresponding respectively to said plurality of groups; each of said plurality of test means simultaneously comparing data read out from said selecting columns belonging to the corresponding group with a predetermined expected data value; and indicating means for providing a result of said plurality of test means, wherein said selecting means comprises means for selecting a single one of said plurality of columns in each group during a normal non-tested operation, each of said plurality of test means comprises a plurality of first amplifying means corresponding respectively to said plurality of columns, second amplifying means, and expected data input means for storing an expected data value, the first amplifying means corresponding to the column selected by said selecting means and said second amplifying means form a current mirror type amplifier during normal reading operation, and each of the first amplifying means corresponding to the columns selected by said selecting means compares data read out from the corresponding column with the expected data value during a testing operation. - View Dependent Claims (2, 3)
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4. A semiconductor memory device comprising:
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a memory array including a plurality of word lines, a plurality of bit line pairs provided to cross said plurality of word lines, and a plurality of memory cells provided at crossings of said word lines and said bit line pairs said plurality of bit line pairs divided into a plurality of groups in an interleaved manner, a plurality of write buses corresponding respectively to said plurality of groups, a plurality of read buses corresponding respectively to said plurality of groups, a plurality of first amplifying means each provided between each of said plurality of bit line pairs and a corresponding read bus, a plurality of second amplifying means corresponding respectively to said plurality of groups, a plurality of expected data input means corresponding respectively to said plurality of groups for storing an expected data value, selecting means for selecting a single one of said plurality of bit line pairs in each group for reading and writing during normal operation, and for simultaneously selecting all bit line pairs in each group during testing operation, connecting means for connecting a bit line pair selected by said selecting means to a corresponding write bus during normal operation, and activation means for activating a first amplifying means corresponding to a selected bit line pair, wherein the activated first amplifying means and said second amplifying means form a current mirror type amplifier during normal reading operation, and wherein each of the activated first amplifying means compares data of the corresponding bit line pair with a corresponding expected data value for providing the comparison result thereof to the corresponding read bus during testing operation. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor memory device comprising:
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first and second memory arrays including a plurality of memory cells arranged in a plurality of rows and columns, said plurality of columns of said memory cell array divided into a plurality of groups in an interleaved manner; switching means for selecting one of said first and second memory arrays; selecting means for simultaneously selecting all columns in each group in a selected row in the selected memory array during testing operation; reading means for reading data stored in the memory cells of the selected row and columns; a plurality of test means corresponding respectively to said plurality of groups; each of said plurality of test means simultaneously comparing data read out from said selected columns belonging to the corresponding group with a predetermined expected data value; and indicating means for providing a result of said plurality of test means, wherein said selecting means comprises means for selecting a single one of said plurality of columns in each group during a normal non-tested operation, each of said plurality of test means comprises a plurality of first amplifying means corresponding respectively to said plurality of columns, second amplifying means, and expected data input means for storing an expected data value, the first amplifying means corresponding to the column selected by said selecting means and said second amplifying means form a current mirror type amplifier during normal reading operation, and each of the first amplifying means corresponding to the columns selected by said selecting means compares data read out from the corresponding column with the expected data value during a testing operation.
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Specification