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Method and apparatus for synchronizing a plurality of processors

  • US 5,384,906 A
  • Filed: 08/23/1993
  • Issued: 01/24/1995
  • Est. Priority Date: 11/09/1987
  • Status: Expired due to Term
First Claim
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1. A computer system comprising:

  • a) a plurality of Central Processing Units (CPUs) each executing a respective instruction stream, the CPUs being clocked independently of one another, each CPU executing its respective instruction stream at a speed which is variable from the speed that each of such other CPUs executes its respective instruction stream, each CPU having at least one processor executing said CPU'"'"'s respective instruction stream during execution cycles and providing first processor events, related to processing said respective instruction stream, spaced apart over plural execution cycles;

    b) each of the CPUs having a cycle counter to count its respective execution cycles and an event counter to count its respective first processor events and provide an event count corresponding to the counted first processor events, each counted first processor event being defined explicitly by a processor instruction which is associated with the counted first processor event the respective instruction stream of such CPU including the same processor instructions that are executed in the respective instruction stream of each of the other CPUseach processor providing an indication of a second processor event in response to its respective CPU'"'"'s cycle counter reaching a selected overflow count, wherein said event counter also counts said second processor events;

    c) wherein each CPU has synchronizing means for halting the execution of the processor instructions in its respective instruction stream upon the respective event counter of such CPU reaching said overflow count, wherein each CPU'"'"'s synchronizing means is coupled to receive the event count of the respective event counters of each of the other CPUs and compares the respective event counts and wherein the respective synchronization means restart each of the respective CPUs to execute the processor instructions in its respective instruction stream from a point in such instruction stream which corresponds to said overflow count when all of the respective event counters have reached said overflow count.

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