Method and apparatus for synchronizing a plurality of processors

• US 5,384,906 A
• Filed: 08/23/1993
• Issued: 01/24/1995
• Est. Priority Date: 11/09/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Horst, Robert W.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Shin, Christopher B.
• Application Number:
  US08/110,328
• Time in Patent Office: 519 Days
• Field of Search: 371/47.1, 371/67.1, 371/68.1, 371/68.2, 371/68.3, 398/550
• US Class Current: 713/375
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/1691 using a quantum
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 11/185 and the voting is itself performed redundantly
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A method and apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow of the event counter forces resynchronization, a cycle counter is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.

Claims

1. A computer system comprising:

a) a plurality of Central Processing Units (CPUs) each executing a respective instruction stream, the CPUs being clocked independently of one another, each CPU executing its respective instruction stream at a speed which is variable from the speed that each of such other CPUs executes its respective instruction stream, each CPU having at least one processor executing said CPU'"'"'s respective instruction stream during execution cycles and providing first processor events, related to processing said respective instruction stream, spaced apart over plural execution cycles;

b) each of the CPUs having a cycle counter to count its respective execution cycles and an event counter to count its respective first processor events and provide an event count corresponding to the counted first processor events, each counted first processor event being defined explicitly by a processor instruction which is associated with the counted first processor event the respective instruction stream of such CPU including the same processor instructions that are executed in the respective instruction stream of each of the other CPUs

each processor providing an indication of a second processor event in response to its respective CPU'"'"'s cycle counter reaching a selected overflow count, wherein said event counter also counts said second processor events;

c) wherein each CPU has synchronizing means for halting the execution of the processor instructions in its respective instruction stream upon the respective event counter of such CPU reaching said overflow count, wherein each CPU'"'"'s synchronizing means is coupled to receive the event count of the respective event counters of each of the other CPUs and compares the respective event counts and wherein the respective synchronization means restart each of the respective CPUs to execute the processor instructions in its respective instruction stream from a point in such instruction stream which corresponds to said overflow count when all of the respective event counters have reached said overflow count.

2. A system according to claim 1 wherein there are three said CPUs.

3. A system according to claim 1 wherein each said CPU has a memory accessable by said CPU but not by the other CPUs.

4. A system according to claim 1 wherein said CPUs access an I/O controller through a vote circuit for outgoing requests.

5. A system according to claim 4 wherein said CPUs receive incoming data from said I/O controller through a path which does not include a vote circuit.

6. A computer system comprising:

a) a plurality of Central Processing Units (CPUs) each executing a respective instruction stream, the CPUs being clocked independently of one another, each CPU executing such stream in independently clocked cycles;

b) each of the CPUs having synchronizing means, including a cycle counter for counting its respective execution cycles and an event counter to count respective preselected CPU events occurring in such CPU during said execution of its respective instruction stream, each counted event being defined explicitly by a processor instruction which is associated with the counted event, the respective instruction stream of such CPU including the same processor instructions that are executed in the respective instruction stream of each of the other CPUs, each processor instruction being executed during its associated execution cycle, wherein said cycle counter has a first overflow count and said event counter has a second overflow count, and wherein the respective CPU issues a synchronizing request to all of said CPUs upon overflow of the cycle counter or the event counter;

wherein each CPU'"'"'s synchronizing means is coupled to receive the event count of the respective event counters of each of the other CPUs and compares the respective event counts and wherein said synchronizing means halts the execution of the processor instructions included in its respective instruction stream, in response to said synchronizing request applied to all of said CPUs, when the respective event counter of such CPU reaches a count that matches the count of the respective event counter of a fastest CPU among all of the CPUs, all of the CPUs being synchronized when the respective synchronizing means of each CPU halts the execution of the processor instructions in its respective instruction stream upon the respective event counter of such CPU reaching a count that is the same as the count reached by the respective event counter of each of such other CPUs, and, after all of the CPUs are synchronized, the respective synchronization means restarts each of the CPUs to execute the processor instructions in its respective instruction stream from a point in such instruction stream which is the same as the point from which each of such other CPUs is restarted to execute the processor instructions in its respective instruction stream.

7. A system according to claim 6 wherein said request is an external interrupt.

8. A system according to claim 6 wherein there are three said CPUs.

9. A system according to claim 6 wherein each said CPU has a memory accessable by said CPU but not by the other CPUs.

10. A computer system comprising:

a) a plurality of Central Processing Units (CPUs) each executing a respective instruction stream, the CPUs being clocked independently of one another to define respective clock cycles for each CPU, each CPU executing such stream at a speed which is variable from the speed that each of such other CPUs executes its respective instruction stream;

b) each of the CPUs having respective synchronizing means, including first counting means to count respective CPU clock cycles and second counting means to count respective CPU events related to the execution of its respective instruction stream, each counted event being defined explicitly by a processor instruction which is associated with the counted event, the respective instruction stream of such CPU including the same processor instructions that are executed in the respective instruction stream of each of such other CPUs, each processor instruction being executed during its associated execution cycle;

wherein each CPU'"'"'s synchronizing means is coupled to receive the event count of the respective event counters of each of the other CPUs and compares the respective event counts and wherein said synchronizing means further include means for receiving an externally-applied synchronization request, said synchronizing means presenting said externally-applied synchronizing request to its respective CPU when the respective second counting means of such CPU reaches a count that matches the count of the respective second counting means of a fastest CPU among all of the CPUs, the synchronizing means also halting execution of instructions in response to said first counting means indicating a selected overflow count when the respective second counting means of such CPU reaches a count that matches the count of the respective second counting means of the fastest CPU among all of the CPUs, all of the CPUs being synchronized when the respective synchronizing means of each CPU halts the execution of the processor instructions in its respective instruction stream upon the respective second counting means of such CPU reaching a count that is the same as the count reached by the respective second counting means of each of such other CPUs, and, after all of the CPUs are synchronized, the respective synchronization means restarting each of the CPUs to execute the same processor instruction in their respective instruction stream and clearing and restarting the respective event counting means and cycle counting means.

11. A system according to claim 10 wherein said synchronizing request is an external interrupt.

12. A system according to claim 10 wherein there are three said CPUs.

13. A system according to claim 10 wherein each said CPU has a memory accessable by said CPU but not by the other CPUs.

14. A system according to claim 10 wherein said CPUs access an I/O controller through a vote circuit for outgoing requests.

15. A system according to claim 14 wherein said CPUs receive incoming data from said I/O controller through a path which does not include a vote circuit.

16. A method for synchronizing a computer system including a plurality of Central Processing Units (CPUs,) each CPU having a respective execution cycle counter, a respective event counter, and a respective synchronizing circuit, each said respective synchronizing circuit being coupled to the respective event counters of all the CPUs, each CPU processing a respective instruction stream including a plurality of processor instructions executed in a particular order in execution cycles clocked independently for each CPU,

the respective instruction stream of each CPU including identical processor instructions;

comprising the steps of;

counting respective execution cycles in said respective execution cycle counter in each CPU and providing a synchronizing request upon overflow of any one thereof;

counting respective events associated with the execution of the respective instruction stream of each CPU in each CPU'"'"'s respective event counter, each counted event being defined explicitly by the processor instruction which is associated with the counted event, each processor instruction being executed during its associated execution cycle;

receiving a synchronizing request in each CPU in response to a respective execution cycle counter overflow in one of said CPUs;

comparing each respective event counter of each of the CPUs in response to a synchronizing request;

halting the execution of the processor instructions included in the respective instruction stream of the fastest CPU by its respective synchronizing circuit in response to said synchronizing request;

continuing execution in each other CPU until such CPU reaches a count matching the count of the respective event counter of the fastest CPU among all of the CPUs and halting execution when the respective counter of such CPU reaches a count matching the count of the respective counter of the fastest CPU among all of the CPUs;

synchronizing all of the CPUs when the respective synchronizing circuit of each CPU halts the execution of the processor instructions in its respective instruction stream upon the respective event counter of such CPU reaching a count that is the same as the count reached by the respective event counter of each of such other CPUs; and

after said synchronizing step restarting all of the CPUs to execute the processor instruction in its respective instruction stream from a point in such instruction stream corresponding to an event count which is the same for each of the CPUs.