Process for fabricating silicon channel structures with variable cross-sectional areas

• US 5,385,635 A
• Filed: 11/01/1993
• Issued: 01/31/1995
• Est. Priority Date: 11/01/1993
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: O'Neill, James F.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/143,774
• Time in Patent Office: 456 Days
• Field of Search: 156/644, 156/647, 156/651, 156/653, 156/657, 156/659.1, 156/661.1, 156/662, 156/646, 347/65
• US Class Current: 216/27
• CPC Class Codes: B41J 2/1404 Geometrical characteristics
• CPC Class Codes: B41J 2/1604 of the edge shooter type
• CPC Class Codes: B41J 2/1623 bonding and adhesion
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: B41J 2/1631 photolithography

Abstract

Three dimensional silicon structures having variable depths such as ink flow channels and reservoirs are fabricated from silicon wafers by a two-step anisotropic etching process from a single side of the wafer. Two different etching masks are formed one on top of the other prior to the initiation of etching with the coarsest mask formed last and used first. Once the coarse anisotropic etching is completed, the coarse etch mask is removed and the finer anisotropic etching is accomplished through the remaining mask. The shape of the mask for the finer anisotropic etching in combination with a predetermined etch time produces a channel having varying depths and widths by controlled undercutting of the mask by the finer anisotropic etching. The preferred embodiment is described using an ink flow directing part of a thermal ink jet printhead where the coarse etching step provides the reservoir and the timed fine etching step provides the ink channels having varying cross-sectional flow areas.

Claims

1. A method of fabricating a three dimensional structure from a silicon wafer having at least one recess with a variable cross-sectional area, the wafer having a thickness and two opposing, substantially parallel surfaces, the fabricating method comprising the steps of:

forming a first layer of etch resistant material on both surfaces of the wafer;

patterning the first layer of etch resistant material on one of the wafer surfaces to delineate a plurality of vias, said vias exposing the surface of the wafer, at least one of the vias having opposing ends and sides with opposing via extensions extending in opposite directions from each via side at a location therealong;

depositing a second layer of etch resistant material on both sides of the wafer and over the first layer of etch resistant material and vias therein;

patterning the second layer of etch resistant material on the same wafer surface as that patterned in the first layer of etch resistant material to produce at least one via within a boundary of one of the vias in said first layer of etch resistant material to expose the silicon wafer surface;

placing the wafer into a first anisotropic etchant to etch coarsely the wafer to produce at least one recess in the wafer through the vias in the second layer of etch resistant material;

removing the second layer of etch resistant material from the wafer to expose the first layer of etch resistant material and the vias in said one surface thereof which expose the wafer surface through said vias;

placing the wafer into a second anisotropic etchant for a time period to produce relatively fine recesses in the exposed wafer surface through the vias in the first layer of etch resistant material, the extensions on opposing sides of said at least one recess causing the second etchant to etch along the {111} crystal planes, so that the second etchant etches under the via extensions of said at least one via in the etch resistant material in opposing directions towards the recess ends, thereby enlarging the recess cross-sectional area intermediate the via ends while the wafer is in the second etchant; and

removing the wafer from the second anisotropic etchant within a time period sufficient to stop the etching under the first layer of etch resistant material to delineate a recess shape having a different cross-sectional area at each end than at a location intermediate the etched recess ends.

2. The method of claim 1, wherein the first layer of etch resistant material is a thermally grown silicon dioxide SiO₂ having a thickness of about 5000-7500 Å

;

wherein the second layer of etch resistant material is silicon nitride (Si₃ N₄) having a thickness of about 0.1-0.2 μ

m; and

wherein each said at least one via in the Si₃ N₄ is positioned within one of the vias in the SiO₂, so that a border exists between the internal boundary of the via in the Si₃ N₄ and the internal boundary of the via in the SiO₂.

3. The method of claim 2, wherein the plurality of vias in the first layer of etch resistant material are a plurality of sets of parallel channel vias and at least one reservoir via for each set of channel vias;

wherein each channel via has said opposing via extensions of extending in opposite directions from each channel via at a location therealong, the reservoir being located adjacent one end of the channel vias and being sized to enable subsequent anisotropic etching through said wafer; and

wherein the at least one via in said second layer of etch resistant material is located within the at least one reservoir vias in the first etch resistant layer, so that a border of second etch resistant material prevents exposure of the first etch resistant material to the anisotropic etchant used to etch through the at least one via in the second etch resistant material.

4. The method of claim 3, wherein the three dimensional structure is a plurality of channel plates integrally formed in said wafer for assembly with a plurality of heater plates integrally formed in a second wafer to produce a quantity of ink jet printheads which may be separated into a plurality of individual printheads by a dicing operation.

5. The method of claim 4, wherein second opposing via extensions extending from opposing sides of each channel via are located at and coincident with the channel via end which is adjacent the reservoir via, said second via extensions extend from the channel via a greater distance than the first opposing via extensions so that after the two etching steps have been completed, the cross-sectional area of the channel recess end adjacent the reservoir recess will be larger than the cross-sectional area of the intermediate portion of the channel recess and the cross-sectional area of the channel recess end opposite the one adjacent the reservoir recess will be smaller than the cross-sectional area of the intermediate portion of the channel recess.

6. The method of claim 4, wherein the patterning of the second layer of etch resistant material includes a second via within a portion of each channel via in the first layer of etch resistant material defined by the channel via and opposing extensions therefrom, so that a boundary of the second layer of etch resistant material prevents the first anisotropic etchant from reaching the first layer of etch resistant material by undercutting of the second layer of etch resistant material.

7. The method of claim 6, wherein each of the channel vias in said first layer of etch resistant material are segmented into a center via having opposing ends and a length and two vias on opposing ends of the center via, the center via containing the extensions which extend the length of the center via, the spacing between the center via and the two vias on opposing ends thereof being a dimension to insure complete undercutting by second anisotropic etchant, so that the subsequently etched channel is connected.

8. The method of claim 6, wherein the patterning of the second layer of etch resistant material includes a third and fourth via within each channel via in the first layer of etch resistant material.