Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output

• US 5,386,128 A
• Filed: 01/21/1994
• Issued: 01/31/1995
• Est. Priority Date: 01/21/1994
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Original Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Inventors: Staller, Craig O., Fossum, Eric R., Cunningham, Thomas J., Krabach, Timothy N.
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/186,185
• Time in Patent Office: 375 Days
• Field of Search: 257/183.1, 257/184, 257/187, 257/189, 257/231, 257/232, 257/233, 257/234, 257/239, 257/257, 257/258, 257/279, 257/291, 257/292
• US Class Current: 257/183.1
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H01L 27/14875 Infrared CCD or CID imagers
• CPC Class Codes: H01L 29/765 Charge-coupled devices peripheral circuits for CCD storage devices G11C19/285

Abstract

A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.

Claims

1. A monolithic semiconductor imager comprising:

a monolithic active layer comprising an indium-based III-V compound semiconductor of a first conductivity type;

an array of focal plane cells on said active layer, each of said focal plane cells comprising;

(a) a photogate over a top surface of said active layer;

(b) a readout circuit dedicated to said focal plane cell comprising plural transistors formed monolithically with said monolithic active layer; and

(c) a single-stage charge coupled device formed monolithically with said active layer between said photogate and said readout circuit for transferring photo-generated charge accumulated beneath said photogate during an integration period to said readout circuit.

2. The imager of claim 1 wherein said photogate comprises:

a thin epitaxial semiconductor layer of a second conductivity type overlying said active layer;

an aperture electrode overlying a peripheral portion of said thin epitaxial semiconductor layer, said aperture electrode being connectable to a photogate bias voltage.

3. The imager of claim 2 wherein said photogate further comprises and etched opening extending through a portion of said active layer and surrounding said aperture electrode to isolate said photogate.

4. The imager of claim 1 wherein said single stage CCD comprises:

a transfer gate electrode overlying said active layer adjacent said photogate and connectable to a transfer control signal;

a collector on said active layer and connectable to a collector bias voltage; and

a screen gate electrode overlying said active layer between said transfer gate electrode and said collector and connectable to a screen gate bias voltage.

5. The imager of claim 4 further comprising thin epitaxial semiconductor layers of said second conductivity type underlying respective ones of said electrodes and overlying said active layer.

6. The imager of claim 5 wherein said collector comprises a collector electrode contacting said active layer.

7. The imager of claim 4 wherein:

a first one of said transistors comprises a field effect reset transistor having a source connected to said collector, a drain connectable to a reset voltage and a gate connectable to a reset control signal; and

a second one of said transistors comprises a field effect output transistor having a gate connected to said collector, a drain connectable to a bias voltage and a source constituting an output node of the cell.

8. The imager of claim 7 wherein said reset transistor and said output transistor are each a junction field effect transistor whose source and drain comprise source and drain electrodes contacting said active layer and whose gate comprises a gate electrode overlying said active layer between said source and drain electrodes.

9. The imager of claim 8 further comprising a thin epitaxial layer of said second conductivity type between said gate electrode and said active layer.

10. The imager of claim 7 wherein said photogate bias voltage is sufficient to produce a first potential well of a first depth under said photogate, said screen gate bias voltage is sufficient to produce a second potential well of a second depth greater than said first depth under said screen gate, said reset voltage is sufficient to produce a third potential well of a third depth greater than said second depth under said collector.

11. The imager of claim 10 wherein said transfer signal has a first state sufficient to produce a potential barrier relative to said first potential well during an integration period and a second state in which said potential barrier relative to said first potential well is removed.

12. The imager of claim 11 wherein said first and second conductivity types are n and p, respectively and wherein said potential well correspond to positive voltages.

13. The imager of claim 12 wherein said III-V compound semiconductor is GaAs, whereby said active layer comprises InGaAs.

14. The imager of claim 13 wherein said thin epitaxial layer is between about 100 and 1000 angstroms thick and wherein said imager is responsive in the shortwave infrared and visible wavelength region.

15. The imager of claim 1 wherein said photogate is on the order of 20 microns in extent.

16. The imager of claim 13 wherein said thin epitaxial layer of said photogate comprises InGaAs doped with on the order of about 10¹⁸ atoms per cubic centimeter of a p-type impurity and said active layer comprises InGaAs doped with on the order of about 10¹⁵ atoms per cubic centimeter of an n-type impurity.

17. The imager of claim 1 further comprising an isolation electrode surrounding at least a portion of said photogate and connectable to an isolation voltage sufficient to produce a potential barrier at least partially surrounding said photogate.

18. The imager of claim 1 wherein said active layer comprises on the order of about 53% indium.

19. The imager of claim 3 further comprising:

(a) a substrate underlying said active layer; and

,

(b) an intermediate monolithic layer of said second conductivity type between said substrate and said active layer.