Multimedia storage system with highly compact memory device

• US 5,386,132 A
• Filed: 11/02/1992
• Issued: 01/31/1995
• Est. Priority Date: 11/02/1992
• Status: Expired due to Term

• Current Assignee: Chun C.D. Wong
• Original Assignee: Chun C.D. Wong
• Inventors: Wong, Chun C. D.
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US07/970,728
• Time in Patent Office: 820 Days
• Field of Search: 257/315, 257/320, 257/321, 257/298, 257/315-326
• US Class Current: 257/316
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5624 Concurrent multilevel programming and programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

Claims

1. A vertical memory cell formed in a trench in a substrate, said vertical memory cell comprising:

a buried source region;

a drain region;

a channel region formed between said buried source region and said drain region;

a floating gate positioned in operative relation to said buried source region, said drain region and said channel region; and

a control gate insulated from said floating gate,

wherein said floating gate includes a first segment positioned vertically in said trench and a second segment positioned horizontally, said first segment being spaced from said drain region by a first distance and said second segment being spaced from said drain region by a second distance less than said first distance.

2. The vertical memory cell of claim 1 wherein said cell is programmed by hot electron injection.

3. The vertical memory cell of claim 1 wherein said second segment is formed above said drain region.

4. The vertical memory cell of claim 3 further comprising an insulating layer formed between said floating gate and said drain region, said channel region, and said source region.

5. The vertical memory cell of claim 4 wherein electrons tunnel from said second segment through said operation.

6. The vertical memory cell of claim 5 wherein said insulation between said first segment and said drain region is approximately 10 nanometers to approximately 20 nanometers thicker than said insulation between said second segment and said drain region.

7. The vertical memory cell of claim 5 wherein substantially no tunneling of electrons from said first segment through said insulating layer to said drain region occurs during an erase operation.

8. The vertical memory cell formed in a substrate comprising:

a buried source region;

a drain region;

a channel region formed between said buried source region and said drain region;

a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region; and

a control gate insulated from said floating gate,

wherein said drain region includes an extended drain region formed from polysilicon.

9. The vertical memory cell of claim 8 wherein said polysilicon is doped.

10. The vertical memory cell of claim 9 wherein said polysilicon is doped with an n+ dopant.

11. The vertical memory cell of claim 10 further comprising an insulating layer formed between said floating gate and said drain region.

12. The vertical memory cell of claim 11 wherein the thickness of said insulating layer is approximately 20 nanometers to approximately 40 nanometers.

13. A vertical memory cell formed in a substrate comprising:

a buried source region;

a drain region;

a channel region formed between said buried source region and said drain region;

a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region;

a control gate insulated from said floating gate; and

an erase/program gate positioned between said drain region and said control gate and in operative relation to said floating gate, wherein said cell is programmed by electrons tunneling from said erase/program gate to said floating gate and erased by electrons tunneling from said floating gate to said erase/program gate.

14. A vertical memory cell formed in a substrate comprising:

a buried source region;

a drain region;

a channel region formed between said buried source region and said drain region;

a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region; and

a control gate insulated from said floating gate; and

an erase/program gate positioned between said drain region and said control gate and in operative relation to said floating gate, wherein said erase/program gate is positioned above said drain region.

15. The vertical memory cell of claim 14 further comprising an insulating layer formed between said erase/program gate and said drain region.

16. The vertical memory cell of claim 15 wherein electrons tunnel from said floating gate to said erase/program gate during an erase operation.

17. The vertical memory cell of claim 16 wherein a predetermined voltage bias condition on said control gate and said erase/program gate allows information in individual memory cells to be erased.

18. The vertical memory cell of claim 17 wherein said predetermined voltage bias condition includes approximately -6 V to approximately -12 V on said control gate and approximately 5 V to approximately 8 V on said erase/program gate.

19. The vertical memory cell of claim 15 wherein said cell is programmed by electrons tunneling from said erase/program gate to said floating gate.

20. The vertical memory cell of claim 19 wherein substantially no tunneling of electrons from said control gate to said floating gate occurs when said cell is programmed and substantially no tunneling of electrons from said floating gate to said control gate occurs when said cell is erased.

21. The vertical memory cell of claim 19 wherein a predetermined voltage bias condition on said control gate and said erase/program gate provides cell-by-cell programmability.

22. The vertical memory cell of claim 21 wherein said predetermined voltage bias condition includes approximately 6 V to approximately 12 V on said control gate and approximately -5 V to approximately -8 V on said erase/program gate.

23. The vertical memory cell of claim 14 wherein said floating gate is positioned between said erase/program gate and said control gate.

24. A vertical memory cell formed in a substrate comprising:

a floating gate transistor formed in a first trench in said substrate;

a series transistor formed in a second trench in said substrate, said second trench vertically aligned with said first trench;

a buried source region;

a drain region;

a channel region formed between said buried source region and said drain region;

a floating gate positioned in operative relation to said buried source region, said drain region, and said channel region; and

a control gate insulated from said floating gate,

wherein said first and second transistors share said channel region, and wherein said floating gate is formed in said first trench.

25. The vertical memory cell of claim 24 wherein said floating gate includes a first segment positioned vertically in said trench and a second segment positioned horizontally, said first segment being spaced from said drain region by a first distance and said second segment being spaced from said drain region by a second distance, wherein said first and second distances are unequal.

26. The vertical memory cell of claim 25 wherein said first distance is greater than said second distance.

27. The vertical memory cell of claim 26 wherein said second segment is formed above said drain region.

28. The vertical memory cell of claim 27 further comprising an insulating layer formed between said floating gate and said drain region, said channel region, and said source region.

29. The vertical memory cell of claim 28 wherein electrons tunnel from said second segment through said insulating layer to said drain region during an erase operation.

30. The vertical memory cell of claim 29 wherein substantially no tunneling of electrons from said first segment through said insulating layer to said drain region occurs during an erase operation.

31. The vertical memory cell of claim 24 wherein said drain region includes an extended drain region to provide a tunneling electrical field enhancement effect.

32. The vertical memory cell of claim 31 wherein said extended drain region is formed from polysilicon.

33. The vertical memory cell of claim 32 wherein said polysilicon is doped with an n+ dopant.

34. The vertical memory cell of claim 33 further comprising an insulating layer formed between said floating gate and said drain region.

35. The memory cell of claim 24 further comprising:

an erase/program gate positioned between said drain region and said control gate and in operative relation to said floating gate.

36. The vertical memory cell of claim 35 wherein said erase/program gate is positioned above said drain region.

37. The vertical memory cell of claim 36 further comprising an insulating layer formed between said erase/program gate and said drain region.

38. The vertical memory cell of claim 37 wherein electrons tunnel from said floating gate to said erase/program gate during an erase operation.

39. The vertical memory cell of claim 38 wherein said cell is programmed by electrons tunneling from said erase/program gate to said floating gate.