Memory cell for associative memory

• US 5,386,379 A
• Filed: 12/29/1992
• Issued: 01/31/1995
• Est. Priority Date: 01/03/1992
• Status: Expired due to Term

• Current Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: France Telecom Etablissement Autonome de Droit Public
• Inventors: Ali-Yahia, Tahar, Dana, Michel
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): GLEMBOCKI, CHRISTOPHE
• Application Number:
  US07/997,931
• Time in Patent Office: 763 Days
• Field of Search: 365/49, 365/189.05, 365/156, 365/190
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

The invention relates to a memory cell for a static associative memory comprising two arrays of transistors, a first array having a data storage function and a second array having a comparison function between the stored data item and a data item applied to the input of the cell, the comparison result being obtained on a selection line S, in which the second array (T1,T2,T3,T4) of transistors is partly formed by the transistors of the first array (T3,T4,T7,T8,T5,T6). The structure of the cell thus has reduced overall dimensions compared with known structures.

Claims

1. Memory cell for a static associative memory comprising two arrays of transistors, a first array having a data storage function and a second array having a comparison function between a stored data item and a data item applied to the cell by bit lines, the comparison result being obtained on a selection line S, characterized in that the second array (T1,T2,T3,T4) of transistors comprises some of the transistors of the first array (T3,T4,T7,T8,T5,T6) connected to be operated by the stored data item to compare the date item applied with the stored data item.

2. Memory cell for a static associative memory according to claim 1, characterized in that the first array comprises four transistors (T3,T4,T7,T8) for storage purposes and two access transistors (T5,T6) connected to the bit lines and to a word line and in that the second array comprises two transistors, the two transistors (T3 and T4) of both arrays being associated with the two transistors of the second array in order to fulfil the comparison function, the data item to be compared being applied to bit lines connected to the two access transistors of the cell and the selection line S is preloaded during reading-writing operations and comparisons.

3. Memory cell for an associative memory according to claim 1, characterized in that the first array comprises four transistors (T3,T4,T7,T8) for the storage and two access transistors (T5,T6) connected to the bit lines and to a word line and in that the second array comprises two transistors, the two transistors (T3 and T4) of both arrays being associated with the two transistors of the second array for fulfilling the comparison function, the data item to be compared being applied to bit lines COMP and COMP connected to the two transistors of the second array.

4. Memory cell according to claim 1, characterized in that it is formed in CMOS technology.

5. Memory cell, according to any one of the preceding claims, characterized in that it comprises a memory plane constituted by an array of memory cells.