Fast multilevel hierarchical routing table lookup using content addressable memory

• US 5,386,413 A
• Filed: 03/19/1993
• Issued: 01/31/1995
• Est. Priority Date: 03/19/1993
• Status: Expired due to Term

• Current Assignee: TTI Inventions A LLC (Intellectual Ventures LLC), National Starch and Chemical Investment Holding Corporation
• Original Assignee: Bell Communications Research, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Wilson, Daniel V., McAuley, Anthony J., Tsuchiya, Paul F.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Kizou, Hassan
• Application Number:
  US08/034,444
• Time in Patent Office: 683 Days
• Field of Search: 370/54, 370/58.2, 370/60, 370/60.1, 370/68.1, 370/85.13, 370/85.14, 370/85.6, 370/94.1, 370/94.2, 370/94.3, 370/110.1, 379/220, 379/229, 379/242, 379/243, 379/244, 379/246, 340/825, 340/52.825, 340/53.825.5, 340/825.51, 364/253, 364/253.1, 364/253.3, 365/49
• US Class Current: 370/392
• CPC Class Codes: H04L 45/04 Interdomain routing, e.g. hierarchical routing
• CPC Class Codes: H04Q 3/0016 Arrangements providing connection between exchanges

Abstract

A switch memory 100 for implementing a multilevel hierarchical routing table in a switch is disclosed. The switch memory 100 includes a plurality of mask circuits 120, 121 and 122, which each correspond to one level of the multilevel hierarchy. Each mask circuit 120, 121 and 122 receives a destination address of an incoming call or packet and masks out portions of the received destination address which do not correspond to the level of the hierarchy with which the mask circuit 120, 121 or 122 is associated. A memory array 130, 131 or 132 corresponding to each mask circuit 120, 121 or 122, is provided which is capable of storing a table of entries including an output port entry and a corresponding destination address of one level of the multilevel hierarchy of destination addresses. Additionally, each memory array 130, 131 or 132 is capable of comparing, in parallel, non-masked portions of the masked destination address outputted from the corresponding mask circuit 120, 121 or 122 with corresponding portions of each destination address of each table entry stored therein. Finally, the switch memory 100 includes a prioritizer 150 for enabling the output of an output port entry of a matched table entry from the memory array 130, 131 or 132, storing destination addresses of the lowest level in the hierarchy, in which a match occurred.

Claims

1. A memory for use in a switch in a communications network for implementing a multilevel hierarchical routing table comprising:

an input for receiving a destination address of a call or packet,

an output for outputting an output port entry indicating a particular output port of said switch for said call or packet,

a plurality of content addressable memories, each content addressable memory associated with one level of said multilevel hierarchical routing table and comprising;

a mask circuit for producing a masked destination address by masking out portions of said destination address of said call or packet received at said input which do not correspond to said one level of said routing table, and

a memory array for storing routing table entries comprising destination addresses and corresponding output port entries for said one level of said multiple hierarchical routing table and for outputting, when each non-masked portion of said masked destination address matches corresponding portions of a destination address of a routing table entry stored in said memory array, an output port entry contained in the matched routing table entry, and

a prioritizer for prioritizing said content addressable memories by selecting, for output from said output, the output port entry outputted from the content addressable memory associated with the lowest level in said hierarchy, in which a match occurred.

2. The memory of claim 1, wherein each memory array is capable of comparing, in parallel, said non-masked portions of said masked destination address to corresponding portions of each destination address of each routing table entry stored in said memory array.

3. The memory of claim 1 wherein said portions masked by said mask circuits correspond to wild card digits of said destination addresses stored in said memory array.

4. The memory of claim 1, wherein each content addressable memory outputs a signal to said prioritizer indicating that a match occurred therein, when said non-masked portions of said masked destination address match corresponding portions of a destination address of a routing table entry stored in said memory array, and wherein said prioritizer, in response to said signals outputted by the addressable memories, selects the output port entry outputted from the content addressable memory associated with the lowest level in the multilevel hierarchy which outputted a signal to said prioritizer.

5. The memory of claim 1 further comprising a plurality of output enable circuits, including one output enable circuit corresponding to each content addressable memory, for receiving an output port entry from said memory array of said corresponding content addressable memory and an output enable control signal from said prioritizer, and for outputting said output port entry from said output in response to said output enable signal received from said prioritizer circuit.

6. A method for routing a call or packet received in a switch in a communications network comprising the steps of:

in each of a plurality of mask circuits, each of said plurality of mask circuits corresponding to one level of a multilevel hierarchical routing table, masking out portions of a destination address of said call or packet, which portions depend on said one level of the hierarchy to which a mask circuit corresponds,

from each of a plurality of memory arrays, with each memory array being associated with one of said mask circuits and storing routing table entries of said corresponding one level in the hierarchy comprising destination addresses and corresponding output port entries, outputting an output port entry of a routing table entry which comprises a destination address having portions which match each corresponding non-masked portion of the masked destination address, and

routing said call or packet onto an output port indicated by an output port entry outputted from the memory array, corresponding to the lowest level in the hierarchy, of said memory arrays which output output port entries.

7. The method of claim 6 further comprising the step of comparing in each memory array, in parallel, each non-masked portion of the masked destination address with a corresponding portion of each destination address of each routing table entry stored in said memory array.

8. The method of claim 6 further comprising the steps of:

from each memory array, if said non-masked portions of the masked destination address match corresponding portions of a destination address of a routing table entry stored in said memory array, outputting an indication signal and said output port entry of the matched routing table entry, and

of said memory arrays which output an indication signal, selecting only the output port entry outputted from the memory array corresponding to the lowest level in the hierarchy.

9. The method of claim 6 wherein each routing table entry stored in each memory array comprises an additional address for addressing a further bloc of data.

10. A memory for use in a central office switch for implementing a multilevel hierarchical routing table comprising a plurality of content addressable memory means, each associated with one level of said multilevel hierarchical routing table and each comprising

mask circuit means for masking out portions of a destination address of a call or packet which do not correspond to said one level of said routing table, and

memory array means for storing routing table entries comprising destination addresses and corresponding output port entries for said one level of said routing table and for comparing non-masked portions of the masked destination address to corresponding portions of each destination address of each routing table entry stored therein.

11. The memory of claim 10 wherein the memory array means of each of the content addressable memory means outputs an indication when there is a match between the non-masked portions of said destination address of said call or packet and the corresponding portions of a destination address of a particular routing table entry stored therein.

12. The memory of claim 11 wherein said memory further comprises a prioritizer for, in response to said indications, giving priority to the content addressable memory means of the lowest level of the hierarchy in which a match occurred.

13. The memory of claim 11 wherein one or more of said content addressable memory means are logical content addressable memories implemented as part of a multiple logical content addressable memory.