Reconfigurable computer interface and method

• US 5,386,518 A
• Filed: 02/12/1993
• Issued: 01/31/1995
• Est. Priority Date: 02/12/1993
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Reagle, Dennis J., Bolstad, Gregory D.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/017,222
• Time in Patent Office: 718 Days
• Field of Search: 395/325, 395/375, 395/425, 395/275, 360/48
• US Class Current: 710/316
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first mechanism is included for generating the state table and a second mechanism is provided for generating the mode control signals with each transmitted to the reconfigurable state machine mechanism. In a preferred embodiment, an initiation logic device generates and downloads a state table and a plurality of mode control signals to a programmable state machine when the reconfigurable computer interface is utilized to connect a new external peripheral device to a signal processing system. The state table defines the characteristics of the state machine and the state machine controls the operation of the reconfigurable computer interface. The programmable state machine utilizes the present state, the state table and the mode control signals to determine the next machine state which provides rapid and convenient reconfigurability of the interface circuit to connect a variety of external devices to the signal processing system. A bus sizing register circuit is included to modify the word size of a plurality of data signals and temporary memory is also included.

Claims

1. A general purpose, reconfigurable parallel-to-parallel interface system for interfacing a first data bus from a first digital subsystem to a second data bus from a second digital subsystem, the interface system comprising:

buffer memory storage means for providing temporary storage of a plurality of data signals transmitted between said first and second subsystems, said buffer memory storage means operating in response to memory storage control signals;

programmable bus sizing means for modifying the word size of a plurality of data signals transmitted between said first and second subsystems in response to bus sizing control signals;

level translating means connected to said first digital subsystem for translating the electrical levels of a plurality of data signals on said first data bus to electrical levels of said reconfigurable system;

reconfigurable state machine means for generating a plurality of interface control signals in accordance with a state table in response to a plurality of external condition signals, said external condition signals including mode control signals, said interface control signals including said memory storage control signals and said bus sizing control signals;

means for establishing a data path through said interface system for connecting said first data bus to said second data bus, said data path comprising said buffer memory storage means, said bus sizing means and said level translating means;

control signal path means for establishing a control signal path between said state machine means and said first digital subsystem, said control signal path being separate from said data path through the interface system and for carrying handshake control signals between said state machine means and said first digital subsystem, said handshake control signals comprising said external condition signals;

host processor means for generating said state table and said mode control signals for said state machine means; and

wherein said state machine means operates autonomously from said host processor means upon receiving said state table and said mode control signals until said host processor generates a fresh state table and mode control signals to reconfigure the interface system.

2. The reconfigurable system of claim 1 wherein said reconfigurable state machine means comprises a downlodable random access memory.

3. The reconfigurable system of claim 2 wherein said downloaded random access memory comprises a storage element register.

4. The reconfigurable system of claim 1 wherein said reconfigurable state machine means comprises a programmable array logic device.

5. The reconfigurable system of claim 1 wherein said host processor means comprises a host microprocessor.

6. The reconfigurable system of claim 1 wherein said level translating means comprises a differential receiver-driver circuit.

7. The reconfigurable system of claim 1 wherein said bus sizing means comprises a plurality of bus sizing registers.

8. The reconfigurable system of claim 1 wherein said buffer storage means includes a buffer having a random access memory.

9. The reconfigurable system of claim 8 further including an address generating means for selecting a storage location within said random access memory for temporarily storing a data word signal.

10. The reconfigurable system of claim 9 wherein said address generating means includes a memory control and address generator.

11. The reconfigurable system of claim 9 wherein said address generating means further includes a memory arbitration means for controlling access of said data word signal to said random access memory.

12. A general purpose, reconfigurable parallel-to-parallel interface system for interfacing a first parallel data bus from an external peripheral device to a second parallel data bus from a signal processing system, the interface system comprising:

buffer memory storage means for providing temporary storage of a plurality of data signals transmitted between said external peripheral device and said signal processing device, said buffer memory storage means operating in response to memory storage control signals;

programmable bus sizing means for modifying the word size of a plurality of data signals transmitted between said external peripheral device and said signal processing device in response to bus sizing control signals;

level translating means connected to said first data bus for translating the electrical levels of a plurality of data signals on said first data bus to electrical levels of said reconfigurable interface system;

reconfigurable state machine means for generating a plurality of interface control signals in accordance with a state table in response to a plurality of external condition signals, said external condition signals including mode control signals, said interface control signals including said memory storage control signals and said bus sizing control signals;

means for establishing a data path through said interface system for connecting said first data bus to said second data bus, said data path comprising said buffer memory storage means, said bus sizing means and said level translating means;

control signal path means for establishing a control signal path between said state machine means and said external peripheral device, said control signal path being separate from said data path through the interface system and for carrying handshake control signals between said state machine means and external peripheral device, said handshake control signals comprising said external condition signals;

host processor means for generating said state table and said mode control signals for said state machine means; and

wherein said state machine means operates autonomously from said host processor means upon receiving said state table and said mode control signals until said host processor generates a fresh state table and mode control signals to reconfigure the interface system.